一、奇分频
一、代码部分
// 奇分频
module odd_div(
input clk,
input rst_n,
output clk_odd_div
);
// 7分频
parameter DIV_NUM = 7;
// 分频计数器
reg [2:0] cnt_div;
wire add_cnt_div;
wire end_cnt_div;
reg clk_div1;
reg clk_div2;
// 分频计数器
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_div <= 0;
end
else if(add_cnt_div)begin
if(end_cnt_div)begin
cnt_div <= 0;
end
else begin
cnt_div <= cnt_div + 1;
end
end
else begin
cnt_div <= cnt_div;
end
end
assign add_cnt_div = 1'b1;
assign end_cnt_div = add_cnt_div && cnt_div == DIV_NUM - 1;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
clk_div1 <= 0;
end
else if(cnt_div == ((DIV_NUM - 1)/2))begin
clk_div1 <= ~clk_div1;
end
else if(cnt_div == DIV_NUM - 1)begin
clk_div1 <= ~clk_div1;
end
end
always @(negedge clk or negedge rst_n)begin
if(!rst_n)begin
clk_div2 <= 0;
end
else if(cnt_div == ((DIV_NUM - 1)/2))begin
clk_div2 <= ~clk_div2;
end
else if(cnt_div == DIV_NUM - 1)begin
clk_div2 <= ~clk_div2;
end
end
assign clk_odd_div = clk_div1 | clk_div2;
endmodule
二、仿真部分
`timescale 1ns/1ns
module odd_div_tb();
//激励信号定义
reg clk ;
reg rst_n ;
//输出信号定义
wire clk_odd_div ;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
odd_div u_odd_div(
/* input */.clk (clk ),
/* input */.rst_n (rst_n ),
/* output */.clk_odd_div (clk_odd_div)
);
//产生时钟
initial clk = 1'b0;
always #(CLOCK_CYCLE/2) clk = ~clk;
//产生激励
initial begin
rst_n = 1'b1;
#(CLOCK_CYCLE*2);
rst_n = 1'b0;
#(CLOCK_CYCLE*2);
rst_n = 1'b1;
#(CLOCK_CYCLE*50);
$stop;
end
endmodule
二、偶分频
一、代码部分
module even_div(
input clk,
input rst_n,
output clk_even_div
);
// 8分频
parameter DIV_NUM = 8;
reg [2:0] cnt_div;
wire add_cnt_div;
wire end_cnt_div;
reg clk_div;
// 分频计数器
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_div <= 0;
end
else if(add_cnt_div)begin
if(end_cnt_div)begin
cnt_div <= 0;
end
else begin
cnt_div <= cnt_div + 1;
end
end
else begin
cnt_div <= cnt_div;
end
end
assign add_cnt_div = 1'b1;
assign end_cnt_div = add_cnt_div && cnt_div == DIV_NUM - 1;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
clk_div <= 0;
end
else if(cnt_div == (DIV_NUM/2) - 1)begin
clk_div <= ~clk_div;
end
else if(cnt_div == DIV_NUM - 1)begin
clk_div <= ~clk_div;
end
end
assign clk_even_div = clk_div;
endmodule
二、仿真部分
`timescale 1ns/1ns
module even_div_tb();
//激励信号定义
reg clk ;
reg rst_n ;
//输出信号定义
wire clk_even_div ;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
even_div u_even_div(
/* input */.clk (clk ),
/* input */.rst_n (rst_n ),
/* output */.clk_even_div (clk_even_div)
);
//产生时钟
initial clk = 1'b0;
always #(CLOCK_CYCLE/2) clk = ~clk;
//产生激励
initial begin
rst_n = 1'b1;
#(CLOCK_CYCLE*2);
rst_n = 1'b0;
#(CLOCK_CYCLE*2);
rst_n = 1'b1;
#(CLOCK_CYCLE*50);
$stop;
end
endmodule
三、D触发器二分频
一、代码部分
module d_div2(
input clk,
input rst_n,
output clk_div2
);
reg clk_div;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
clk_div <= 0;
end
else begin
clk_div <= ~clk_div;
end
end
assign clk_div2 = clk_div;
endmodule
二、仿真部分
`timescale 1ns/1ns
module d_div2_tb();
//激励信号定义
reg clk ;
reg rst_n ;
//输出信号定义
wire clk_div2;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
d_div2 u_d_div2(
/* input */.clk (clk ),
/* input */.rst_n (rst_n ),
/* output */.clk_div2 (clk_div2 )
);
//产生时钟
initial clk = 1'b0;
always #(CLOCK_CYCLE/2) clk = ~clk;
//产生激励
initial begin
rst_n = 1'b1;
#(CLOCK_CYCLE*2);
rst_n = 1'b0;
#(CLOCK_CYCLE*2);
rst_n = 1'b1;
#(CLOCK_CYCLE*50);
$stop;
end
endmodule
四、总结
马上就要面试了,这种基础的题目得会,奇分频我第一时间也是懵逼的,不会啊,所以就要去看去学。