用verilog实现卖报纸机

题目：画状态机，接收1，2，5分钱的卖报纸机，每份报纸5分钱。
程序代码：

module maibaoji(
input clk,
input rst,
input [2:0]din,
output reg [1:0]dout
);

parameter idle = 0,
st1 = 1,
st2 = 2,
st3 = 3,
st4 = 4,
st5 = 5,
st6 = 6;
reg [2:0]current_state,next_state;

always@(posedge clk or negedge rst)begin
if(!rst)
current_state <= idle;
else
current_state <= next_state;
end

always@(next_state or current_state or din or dout)begin
case(current_state)
idle:
if(din == 3’b100)
next_state = st1;
else if(din == 3’b010)
next_state = st2;
else if(din == 3’b001)
next_state = st5;
else if(din == 3’b000)
next_state = idle;
st1:
if(din == 3’b100)
next_state = st2;
else if(din == 3’b010)
next_state = st3;
else if(din == 3’b000)
next_state = st1;
st2:
if(din == 3’b100)
next_state = st3;
else if(din == 3’b010)
next_state = st4;
else if(din == 3’b000)
next_state = st2;
st3:
if(din == 3’b100)
next_state = st4;
else if(din == 3’b010)
next_state = st5;
else if(din == 3’b000)
next_state = st3;
st4:
if(din == 3’b100)
next_state = st5;
else if(din == 3’b010)
next_state = st6;
else if(din == 3’b000)
next_state = st4;
st5:
if(din == 3’b100)
next_state = st1;
else if(din == 3’b010)
next_state = st2;
else if(din == 3’b000)
next_state = idle;
st6:
if(din == 3’b100)
next_state = st2;
else if(din == 3’b010)
next_state = st3;
else if(din == 3’b000)
next_state = st1;
default:
next_state = idle;
endcase
end
always@(posedge clk)begin
if(next_state == 5)
dout <= 2’b10;
else if (next_state == st6)
dout <= 2’b11;
else
dout <= 2’b00;
end
endmodule

图：