场景:使用ILA监测双时钟FIFO。
当ILA输入时钟是FIFO写入时钟cmos_clk(72MHz),而监测的FIFO读出时钟是lcd_clk(50Hz),则可能导致竞争冒险,比如rd_data_count[9:0]是根据读出时钟上升沿变化,却在写入时钟上升沿被ILA读取。
按理0fe->0ff->100->101
实际0fe->0ff->181->100->101
观察ILA输出波形,低第一位和高第三位来不及拉低。
附上rd_data_count的官方提示:
Note: If a read operation occurs on a rising clock edge of rd_clk/clk, that read is reflected on the rd_data_count signal following the next rising clock edge. A write operation on the wr_clk/clk clock domain may take a number of clock cycles before being reflected in the rd_data_count