FPGA入门学习笔记（十四）Vivado实现数码管段码显示以及动态扫描

NonnettaWu

已于 2023-05-17 20:04:29 修改

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分类专栏： FPGA 文章标签： fpga开发学习

于 2023-03-15 20:44:04 首次发布

本文链接：https://blog.csdn.net/weixin_45463952/article/details/129545033

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硬件结构

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软件架构

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仿真波形

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设计文件程序

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`timescale 1ns/1ns
module hex8_2(
    Clk,
    Reset_N,
    Disp_Data,
    Sel,
    DisPlay
    );
    input Clk;
    input Reset_N;
    input [31:0]Disp_Data;
    output reg [7:0]Sel;
    output reg [7:0]DisPlay;
    
    reg clk_1k;
    reg [15:0]div_cnt;
    
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        div_cnt <= 0;
    else if(div_cnt >= 49999)
        div_cnt <= 0;
    else
        div_cnt <= div_cnt + 1'd1;
    
    // clk_1k采用使能时钟，避免使用门控时钟
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        clk_1k <= 0;
    else if(div_cnt == 49999)
        clk_1k <= 1'b1;
    else
        clk_1k <= 0;
    
    
    reg [2:0]Num;
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        Num <= 0;
    else if(clk_1k)
        Num <= Num + 1'd1;
    
    // 3_8译码器
    always@(posedge Clk)
        case(Num)
            3'b000: Sel = 8'b0000_0001;
            3'b001: Sel = 8'b0000_0010;
            3'b010: Sel = 8'b0000_0100;
            3'b011: Sel = 8'b0000_1000;
            3'b100: Sel = 8'b0001_0000;
            3'b101: Sel = 8'b0010_0000;
            3'b110: Sel = 8'b0100_0000;
            3'b111: Sel = 8'b1000_0000;
        endcase
    
    // 8选1多路器
    reg [3:0]Disp_tmp;
    always@(posedge Clk)
        case(Num)
            3'b000: Disp_tmp = Disp_Data[3:0];
            3'b001: Disp_tmp = Disp_Data[7:4];
            3'b010: Disp_tmp = Disp_Data[11:8];
            3'b011: Disp_tmp = Disp_Data[15:12];
            3'b100: Disp_tmp = Disp_Data[19:16];
            3'b101: Disp_tmp = Disp_Data[23:20];
            3'b110: Disp_tmp = Disp_Data[27:24];
            3'b111: Disp_tmp = Disp_Data[31:28];
        endcase
    always@(posedge Clk)
        case(Disp_tmp)
            0:  DisPlay = 8'hc0;
            1:  DisPlay = 8'hf9;
            2:  DisPlay = 8'ha4;
            3:  DisPlay = 8'hb0;
            4:  DisPlay = 8'h99;
            5:  DisPlay = 8'h92;
            6:  DisPlay = 8'h82;
            7:  DisPlay = 8'hf8;
            8:  DisPlay = 8'h80;
            9:  DisPlay = 8'h90;
            10: DisPlay = 8'h88;
            11: DisPlay = 8'h83;
            12: DisPlay = 8'hc6;
            13: DisPlay = 8'ha1;
            14: DisPlay = 8'h86;
            15: DisPlay = 8'h8e;
        endcase  
endmodule

`timescale 1ns / 1ns

module hex8_test(
        Clk,
        Reset_N,
        Sel,
        DisPlay
    );
    input Clk;
    input Reset_N;
    output [7:0]Sel;
    output [7:0]DisPlay;
    wire [31:0]Disp_Data;
    
    hex8_2 hex8_2(
        Clk,
        Reset_N,
        Disp_Data,
        Sel,
        DisPlay
    );
    assign Disp_Data = 32'h13569bdf;
endmodule

仿真文件程序

`timescale 1ns / 1ns

module hex8_tb();
    reg Clk;
    reg Reset_N;
    reg [31:0]Disp_Data;
    wire [7:0]Sel;
    wire [7:0]DisPlay;
    hex8_2 hex8_2(
            Clk,
            Reset_N,
            Disp_Data,
            Sel,
            DisPlay
        );
    initial Clk = 0;
    always #10 Clk = !Clk;
    initial begin
        Reset_N <= 0;
        Disp_Data <= 32'h00000000;
        #201;
        Reset_N <= 1;
        Disp_Data <= 32'h12345678;
        #10000000;
        Disp_Data <= 32'h9abcdef0;
        #10000000;       
        $stop;
    end
endmodule