vxworks7.0 zynq qspi编程详解

zynq7000系列qspi初始化配置如下：

1. Configure Clocks. Refer to section 12.4.1 Clocks.

The clock enable,

PLL select,

and divisor setting are programmed using the Register (slcr) LQSPI_CLK_CTRL

QSPI时钟一般为200000000HZ，计算分频系数，时钟源选择PLL/IO为1000000000HZ，ARMPLL为1333000000HZ，DDRPLL为1067000000hz，分频系数为1000000000/200000000=5
slcr.LQSPI_CLK_CTRL register.

Register (slcr) LQSPI_CLK_CTRL
Register LQSPI_CLK_CTRL Details

Name Relative Address Absolute Address Width Access Type Reset Value Description

LQSPI_CLK_CTRL 0x0000014C 0xF800014C 32 bits rw 0x00002821 Quad SPI Ref Clock Control

 

Field Name	Bits	Type	Reset Value	Description
reserved	31:14	rw	0x0	Reserved. Writes are ignored, read data is zero.
DIVISOR	13:8	rw	0x28	Divisor for Quad SPI Controller source clock.
reserved	7:6	rw	0x0	Reserved. Writes are ignored, read data is zero.
SRCSEL	5:4	rw	0x2	Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
reserved	3:1	rw	0x0	Reserved. Writes are ignored, read data is zero.
CLKACT	0	rw	0x1	Quad SPI Controller Reference Clock control 0: disable, 1: enable

2. Configure Tx/Rx Signals. Refer to section 12.5.2 MIO Programming.

a、是能mio1作为片选，IO类型LCMOS3.3,使能内部上拉

b、设置mio2,mio3,mio4,mio5,mio6,mio8,不使能内部上拉，其他一样

 

3. Reset the Controller. Refer to section 12.4.2 Resets.

a. Set controller resets. Write a 1 to the slcr.LQSPI_RST_CTRL[QSPI__REF_RST and
LQSPI_CPU1X_RST] bit fields.
b. Clear controller resets. Write a 0 to the slcr.LQSPI_RST_CTRL[QSPI__REF_RST and
LQSPI_CPU1X_RST] bit fields.

4. Configure the Controller. Refer to section 12.3.1 Configuration.

a、配置qspi使能寄存器XQSPIPS_ER_OFFSET,不使能SPI

b、配置中断寄存器，关所有中断

c、配置接受RX_thres_REG和发送阈值TX_FIFO Threshold Register

d、配置寄存器设置时钟spi通信分频系数，200000000/100000000 = 2，参照DTS配置

 

 qspi0: qspi@e000d000 
            {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "xlnx,zynq7k-qspi";
            reg = <0xE000D000 0x100>,
                  <0xF8000000 0x800>;
            interrupts = <51>; 
            interrupt-parent = <&intc>;
               spiflash@0
		        {
			        compatible = "s25Fl256Sflash";
			        reg = <0>;
			        data-lines = <4>;
			        chip-number = <1>;
			        spi-max-frequency = <100000000>;
		        };
            };

 e、关spi使能，配置主机模式、flash接口模式，分频系数，手动传输模式，fifo宽度32，开spi使能

5、与qspi设备通信

In Manual mode, the user controls the start of data transmission. In this case, software either writes
the entire transmission sequence to the TxFIFO or until the TxFIFO is full. Upon writing of the
Man_start_en bit, the controller takes over, asserts CS, shifts data out of the TxFIFO and into the
RxFIFO, controls the input/ouput state of the MIO as appropriate, and terminates the sequence when
the TxFIFO is empty by de-asserting CS. The maximum number of bytes per command sequence in
this mode is limited by the depth of the TxFIFO of 252 bytes.
先写数据到TXD，然后使能发送开始位启动传输