Lemmings3

最新推荐文章于 2024-03-27 16:40:13 发布

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最新推荐文章于 2024-03-27 16:40:13 发布

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分类专栏： verilog 文章标签： verilog

本文链接：https://blog.csdn.net/weixin_45614076/article/details/121619782

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module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    reg [2:0] state,next_state;
    parameter left=0, dig_l = 1, fall_l=2, right=3, dig_r=4,fall_r=5;
    
    always @(*)
        begin
            case(state)
                left: begin
                    if(!ground)
                        next_state = fall_l;
                    else if(dig)
                        next_state = dig_l;
                    else
                        next_state = bump_left ? right : left;
                end
                dig_l:begin
                    if(!ground)
                        next_state = fall_l;
                    else
                        next_state = dig_l;
                end
                
                fall_l:begin
                    if(!ground)
                        next_state = fall_l;
                    else
                        next_state = left;
                end
                right:begin
                    if(!ground)
                        next_state = fall_r;
                    else if(dig)
                        next_state = dig_r;
                    else
                        next_state = bump_right ? left : right;
                end
                dig_r:begin
                    if(!ground)
                        next_state = fall_r;
                    else
                        next_state = dig_r;
                end
                fall_r:begin
                    if(!ground)
                        next_state = fall_r;
                    else
                        next_state = right;
                end
            endcase
        end
    
    always @(posedge clk, posedge areset)
        begin
            if(areset)
                state <= left;
            else
                state <= next_state;
        end

    assign walk_left = (state == left);
    assign walk_right = (state == right);
    assign aaah = (state == fall_l | state == fall_r);
    assign digging = (state == dig_l | state == dig_r);
endmodule