module top_module (
input clock,
input a,
output p,
output q );
reg state;
// for q
always @(negedge clock)
begin
q <= a;
end
always @(negedge clock)
begin
state <= a;
end
assign p= clock ? a : state;
endmodule
05-02
266
![](https://csdnimg.cn/release/blogv2/dist/pc/img/readCountWhite.png)
03-21
10-27
333
![](https://csdnimg.cn/release/blogv2/dist/pc/img/readCountWhite.png)
“相关推荐”对你有帮助么?
-
非常没帮助
-
没帮助
-
一般
-
有帮助
-
非常有帮助
提交