module top_module (
input clock,
input a,
output p,
output q );
reg state;
// for q
always @(negedge clock)
begin
q <= a;
end
always @(negedge clock)
begin
state <= a;
end
assign p= clock ? a : state;
endmodule
Sim/circuit8
最新推荐文章于 2024-05-02 16:58:52 发布