数码管亮灯显示（FPGA学习笔记四）

---

前言

用按键驱动数码管

---

提示：以下是本篇文章正文内容，下面案例可供参考

一、驱动电路

DIG决定数码管位置，A~G决定7位的显示，DP决定小数点

---

二、设计文件

1.设计思路

先分频，使数码管常亮，然后检测按键，将按键的值赋值给数码管。

---

2.设计代码

module v_smg(
    input clk,
    input [15:0]sw,
    output [7:0]seg,
    output [3:0]DIG
    );
    reg clkDiv=0;
    reg [31:0]clkCnt=0;
    reg [2:0]bit=0;
    reg [3:0]disp_bat;
    reg [5:0]DIG;
    reg [7:0]seg;
    parameter clkNum=25000;
    always@(posedge clk) begin
        if (clkCnt==clkNum) begin
            clkDiv=~clkDiv;
            clkCnt=0;
        end
        else begin
            clkCnt=clkCnt+1;
        end
    end
    always@(posedge clkDiv) begin
        if(bit>5) begin
            bit=0;
        end
        else begin
        bit=bit+1;
        end
        case (bit)
            3'h0: 
            begin
            disp_bat=sw[3:0];
            DIG=6'b111110;
            end
            3'h1: 
            begin
            disp_bat=sw[7:4];
             DIG=6'b111101;
            end
            3'h2: 
            begin
            disp_bat=sw[11:8];
            DIG=6'b111011;
            end
            3'h3: 
            begin
            disp_bat=sw[15:12];
            DIG=6'b110111;
            end
            default: 
            begin
            disp_bat=sw[3:0];
             DIG=6'b111111;
            end
       endcase
  end
       always@(disp_bat) begin
            case(disp_bat) 
               4'h0: seg=8'h3f;
               4'h1: seg=8'h06;     
               4'h2: seg=8'h5b;
               4'h3: seg=8'h4f;
               4'h4: seg=8'h66;
               4'h5: seg=8'h6d;
               4'h6: seg=8'h7d;
               4'h7: seg=8'h07; 
               4'h8: seg=8'h7f;
               4'h9: seg=8'h6f;
               4'ha: seg=8'h88;
               4'hb: seg=8'h83;
               4'hc: seg=8'hc6;
               4'hd: seg=8'ha1;
               4'he: seg=8'h86;
               4'hf : seg=8'h8e;
            endcase
       end
endmodule

二、添加约束

代码如下（示例）：

## CLK
set_property PACKAGE_PIN D4 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]  
## switches 
set_property PACKAGE_PIN F3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]  
set_property PACKAGE_PIN H4 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]  
set_property PACKAGE_PIN N4 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]  
set_property PACKAGE_PIN R2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]  
set_property PACKAGE_PIN R3 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]  
set_property PACKAGE_PIN P4 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]  
set_property PACKAGE_PIN R5 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]  
set_property PACKAGE_PIN P6 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]  
set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]  
set_property PACKAGE_PIN T7 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]  
set_property PACKAGE_PIN T8 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]  
set_property PACKAGE_PIN T9 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]  
## SEG  A~G DP=seg[0]~seg[7]
set_property PACKAGE_PIN P11 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN N12 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN L14 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN K13 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN K12 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN P13 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN M14 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN L13 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
##  DIG
set_property PACKAGE_PIN G12 [get_ports {DIG[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[0]}]
set_property PACKAGE_PIN H13 [get_ports {DIG[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[1]}]
set_property PACKAGE_PIN M12 [get_ports {DIG[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[2]}]
set_property PACKAGE_PIN N13 [get_ports {DIG[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[3]}]
set_property PACKAGE_PIN N14 [get_ports {DIG[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[4]}]
set_property PACKAGE_PIN N11 [get_ports {DIG[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIG[5]}]
endmodule

三、错误信息

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs: seg[7] (LVCMOS18, requiring VCCO=1.800) and sw[0] (LVCMOS33, requiring VCCO=3.300)

网上的说是默认电平冲突，修改默认电平。但实际的错误原因是{DIG[5]}等内容书写不规范

数码管只显示0和1，没有其他数字

设计文件中忘记规定disp_bat的位宽，使得disp_bat默认为1位，非一位的变量一定要规定位宽！