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最新推荐文章于 2024-06-15 16:47:43 发布

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文章标签： systemverilog

本文链接：https://blog.csdn.net/weixin_45645937/article/details/116743159

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`timescale 1ns / 1ps

module edge_det (
    input           	sys_clk,
    input       	sys_rst_n,
    input		i_btn,
    output logic	posedge_flag,
    output logic	negedge_flag
    )
    
       reg    data_in_d1;
	   reg    data_in_d2;
       reg    data_in_d0;
		always_ff@(posedge sys_clk,negedge sys_rst_n)
		begin
		    if(sys_rst_n==0)
			    begin 
                data_in_d0 <= 1'b0;
                data_in_d1 <= data_in_d0 ; 
			    data_in_d2 <= data_in_d0; 
                 
		    end 
		    else    begin 
                   
				    data_in_d1 <= i_btn; 
				    data_in_d2 <= data_in_d1;
			end 
		end 
            
		assign	 posedge_flag =(~data_in_d2  & (data_in_d1));//上升沿
		assign	 negedge_flag = (data_in_d2 &  (~data_in_d1));//下降沿
endmodule