1.Keep state registers and next state logic in separate blocks.
2.Define states parameters in Verilog.
3.Use binary encoding for small state(less than 8 states) machines.
4.Use modified one-hot state encoding for large.
5.Divide very large(more than 32 states) state machine into multiple smaller ones.
IC设计 Design Rule学习(1)--状态机Coding Style
最新推荐文章于 2023-06-02 20:56:16 发布