Verilog刷题HDLBits——Countbcd

题目描述

Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.

You may want to instantiate or modify some one-digit decade counters.

代码

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    
    assign ena[1] = 1'b1&&q[3:0]==9;
    assign ena[2] = ena[1]&&q[7:4]==9;
    assign ena[3] = ena[2]&&q[11:8]==9;
    bcd_count bcd1(clk,reset,1'b1,q[3:0]);
    bcd_count bcd2(clk,reset,ena[1],q[7:4]);
    bcd_count bcd3(clk,reset,ena[2],q[11:8]);
    bcd_count bcd4(clk,reset,ena[3],q[15:12]);

endmodule

module bcd_count (input clk,reset,ena,output[3:0] q);
    always@(posedge clk)
        begin
            if(reset||(ena&&q==9))
                q<=0;
            else
                if(ena)
                    q<=q+1;
        end
endmodule

结果