Verilog刷题HDLBits——Fsm hdlc

题目描述

Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a “flag” that indicate frame boundaries. To avoid the data stream from accidentally containing “flags”, the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.

Create a finite state machine to recognize these three sequences:

• 0111110: Signal a bit needs to be discarded (disc).
• 01111110: Flag the beginning/end of a frame (flag).
• 01111111…: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input were 0.

Here are some example sequences that illustrate the desired operation.

Implement this state machine.

代码

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter none=0,one=1,two=2,three=3,four=4,five=5,six=6,discard=7,fg=8,error=9;
    reg[3:0] state,next_state;
    
    always@(*)
        case(state)
            none:	next_state=in?one:none;
            one:	next_state=in?two:none;
            two:	next_state=in?three:none;
            three:	next_state=in?four:none;
            four:	next_state=in?five:none;
            five:	next_state=in?six:discard;
            six:	next_state=in?error:fg;
            discard:next_state=in?one:none;
            fg:		next_state=in?one:none;
            error:	next_state=in?error:none;
        endcase
    
    always@(posedge clk)
        if(reset)
            state<=none;
    	else
            state<=next_state;
    
    assign disc = (state==discard);
    assign flag = (state==fg);
    assign err = (state==error);

endmodule

结果