Verilog 刷题-Fsm hdlc

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    reg [3:0]state;
    reg [3:0]next_state;
    parameter w=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,dis=7,fla=8,er=9;
    always@(*)begin 
        case(state)
            w:next_state=in?s1:w;
            s1:next_state=in?s2:w;
            s2:next_state=in?s3:w;
            s3:next_state=in?s4:w;
            s4:next_state=in?s5:w;
            s5:next_state=in?s6:dis;
            s6:next_state=in?er:fla;
            dis:next_state = in?s1:w;
            fla:next_state = in?s1:w;
            er:next_state = in?er:w;
        endcase
    end
    always@(posedge clk)begin 
        if(reset)state <=w;
        else state<=next_state;
    end
    assign disc = (state == dis);
    assign flag = (state == fla);
    assign err = (state == er);
    
endmodule