题目描述
You are provided a module with the following declaration:
module dut ( input clk ) ;
Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module’s clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.
代码
module top_module ( );
parameter time_period = 10;
reg clk;
initial clk = 0;
always #(time_period/2) clk=~clk;
dut dut1(clk);
endmodule