verilog testbench编写笔记

1 . initial模块赋值时注意在时钟上升沿打入数据

initial 
begin
          ax = 16'd0;
          ay = 11'd0;
  bx = 16'd0;
  by = 11'd0; 
  enb1 = 1'b0;  
  enb2 = 1'b0;  
  enb3 = 1'b0;
  accum = 1'b0;
  loadconst = 1'b0;

#110;
@(posedge clk1)
          ax = 16'd2;
          ay = 11'd3;
  bx = 16'd3;
  by = 11'd2;
  enb1 = 1'b1;  
  enb2 = 1'b1;  
  enb3 = 1'b1;
  accum = 1'b1;
  loadconst = 1'b0;  

end

2 . tb中时钟设置注意

tb中仿真时间常数必须带小数点，没有小数点时rtl中时钟周期除2是整除，和参数设置时钟出现出入，如下：

clk_200m = 200Mhz

   parameter   CLK_200M0 = 5.0;

   reg clk_200m = 1'b0;

   always #(CLK_200M0/2)    clk_200m = ~clk_200m ;

clk_200m = 250Mhz

   parameter   CLK_200M0 = 5;

   reg clk_200m = 1'b0;

   always #(CLK_200M0/2)    clk_200m = ~clk_200m ;

3.IO函数

3.1 $display,$fdisplay格式化输出

二者功能类似，只是第一个是打印输出，第二个是写文件

具体格式化输出如下实例：

代码：
    $display("========test=====0=== %5h", 20'h20000);
    $display("========test=====1=== %5h", 20'h00200);
    $display("========test=====2=== %5h", 32'h02120000);
    $display("========test=====3=== %5h", 32'h21240000);        
    $display("========test=====00=== %h", 20'h20000);
    $display("========test=====11=== %h", 20'h00200);
    $display("========test=====22=== %h", 32'h02120000);
    $display("========test=====33=== %h", 32'h21240000); 


输出：

    # ========test=====0=== 20000
    # ========test=====1=== 00200
    # ========test=====2=== 2120000
    # ========test=====3=== 21240000
    # ========test=====00=== 20000
    # ========test=====11=== 00200
    # ========test=====22=== 02120000
    # ========test=====33=== 21240000