Verilog HDLBits4-testbench

Tb/clock

You are provided a module with the following declaration:

module dut ( input clk ) ;

Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.

 

生成周期为10ps的时钟信号

`timescale 1ps/1ps
module top_module ( );
	reg clk;
    dut a1(clk);
    initial begin
        clk=1'b0;
    end
    always begin
        # 5
        clk=~clk;
    end
endmodule

 Tb/tb1

Create a Verilog testbench that will produce the following waveform for outputs A and B

 

这个testbench不能用always+延时，否则会重复输出，可以用initial完成

`timescale 1ps / 1ps
module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A=1'b0;
        B=1'b0;
        # 10
        A=~A;
        # 5
        B=~B;
        # 5
        A=~A;
        # 20
        B=~B;
    end

endmodule

 Tb/and

You are given the following AND gate you wish to test:

module andgate (
    input [1:0] in,
    output out
);

Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram

 

虽然可以用循环来实现4种输入情况，但使用always（循环）时会报错

// error answer!
`timescale 1ps / 1ps
module top_module();
    reg[1:0]in;
    reg out;
    andgate a1(
        .in(in),
        .out(out)
    );
    initial begin
        in=2'b00;
    end
    always begin
        # 10
        in[0]=~in[0];
        # 10
        in[1]=~in[1];
        in[0]=~in[0];
    end
endmodule

 只能用initial了

`timescale 1ps / 1ps
module top_module();
    reg[1:0]in;
    reg out;
    andgate a1(
        .in(in),
        .out(out)
    );
    initial begin
        in=2'b00;
        # 10
        in[0]=~in[0];
        # 10
        in[1]=~in[1];
        in[0]=~in[0];
        # 10
        in[0]=~in[0];
    end

endmodule

Tb/tb2

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

initial和always的延时互不干扰~

module top_module();
	reg clk,in,out;
    reg[2:0] s;
    q7 a1(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
    );
    initial begin
		clk=1'b0;
		in=1'b0;
        s=3'd2;
        # 10
        s=3'd6;
        # 10
        in=~in;
        s=3'd2;
        # 10
        in=~in;
        s=3'd7;
        # 10
        in=~in;
        s=3'd0;
        # 30
        in=~in;
    end
    always begin
        # 5
        clk=~clk;
    end
endmodule

Tb/tff

You are given a T flip-flop module with the following declaration:

module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);

Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the "1" state.

reset=1时同步置位

因为要求同步reset，所以t的值不能通过延时改变，而需要根据clk边沿变化

module top_module ();
	reg clk,reset,t,q;
    tff a1(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );
    initial begin
        clk=1'b0;
        reset=1'b0;
        t=1'b0;
        # 3
        reset=~reset;
        # 5
        reset=~reset;
    end
    always begin
        # 5
        clk=~clk;
    end
    always@(posedge clk) begin
        if(reset)
            t=1'b1;
        else
            t=1'b0;
    end
endmodule