Verilog刷题HDLBits——Tb/tb1 题目描述代码结果 题目描述 Create a Verilog testbench that will produce the following waveform for outputs A and B: 代码 module top_module ( output reg A, output reg B );// // generate input patterns here initial begin A=0; B=0; #10 A=1; #5 B=1; #5 A=0; #20 B=0; end endmodule 结果