Verilog练习：HDLBits笔记19

五、Reading Simulations

Writing Testbenches

1、Clock

Problem Statement：

You are provided a module with the following declaration:

module dut ( input clk ) ;

Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.

module top_module ( );

    reg clk;
    
    initial begin
    	clk = 1'b0; 
    end
    
    always #5 clk =~clk;
    
    dut instance1(.clk(clk));
    
endmodule

2、Testbench1

Problem Statement：

Create a Verilog testbench that will produce the following waveform for outputs A and B:

module top_module ( output reg A, output reg B );
	
    initial begin
		A <= 1'b0;
        B <= 1'b0;
        #10
        A <= 1'b1;
        B <= 1'b0;
        #5
        A <= 1'b1;
        B <= 1'b1;     
        #5
        A <= 1'b0;
        B <= 1'b1; 
        #20
        A <= 1'b0;
        B <= 1'b0;          
    end

endmodule

3、AND gate

Problem Statement：

You are given the following AND gate you wish to test:

module andgate (
    input [1:0] in,
    output out
);

Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram:

module top_module();
	
    reg [1:0]in;
    wire out;
    
    initial begin
        in <= 2'b00;
        #10
        in <= 2'b01;
        #10
        in <= 2'b10;
        #10
        in <= 2'b11;    
    end
    
    andgate instance1(.in(in), .out(out));
    
endmodule

4、Testbench2

Problem Statement：

The waveform below sets clk, in, and s:

 

Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

module top_module();

    reg clk;
    reg in;
    reg[2:0]s;
    
    wire out;
    
    initial begin
    	clk <= 1'b0;
    end
    always #5 clk <= ~clk;
    
    initial begin
    	in <= 1'b0;
        #20
        in <= 1'b1;
        #10
        in <= 1'b0;
        #10
        in <= 1'b1;   
        #30
        in <= 1'b0;           
    end
    
    initial begin
    	s <= 3'd2;
        #10
        s <= 3'd6;
        #10
        s <= 3'd2;
        #10
        s <= 3'd7;   
        #10
        s <= 3'd0;         
    end  
    
    q7 instance1(.clk(clk), .in(in), .s(s), .out(out));
    
endmodule

5、T flip-fiop

Problem Statement：

You are given a T flip-flop module with the following declaration:

module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);

Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the "1" state.

module top_module ();
	
    reg clk;
    reg reset;
    reg t;
    
    wire q;
    
    tff instance1(.clk(clk), .reset(reset), .t(t), .q(q));
    
	initial begin
    	clk <= 1'b0;
    end
    always #5 clk <= ~clk;
    
    initial begin
    	reset <= 1'b1;
        #10
        reset <= 1'b0;
        t <= 1'b1;
    end

endmodule