HDLbits答案（6 Verification: Reading Simulation + 7 Verification: Writing Testbenches)

6 Verification: Reading Simulation

6.1 Finding bugs in code

6.1.1 Mux（Bugs mux2）

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out = sel ? a : b;

endmodule

6.1.2 NAND（Bugs nand3）

module top_module (input a, input b, input c, output out);//
	
    wire out_tmp;
    
    andgate inst1 (  out_tmp, a, b, c, 1'b1, 1'b1 );
    assign out = ~out_tmp;
    
endmodule

6.1.3 Mux（Bugs mux5）

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux0, mux1;
    mux2 u1_mux2 ( sel[0],    a,    b, mux0 );
    mux2 u2_mux2 ( sel[0],    c,    d, mux1 );
    mux2 u3_mux2 ( sel[1], mux0, mux1,  out );

endmodule

6.1.4 Add/sub（Bugs addsubz）

module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [70] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out == 8'd0)
            result_is_zero = 1;
        else begin
            result_is_zero = 0;
        end
    end

endmodule

6.1.5 Case statement（Bugs case）

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

    always @(*)begin
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: out = 0;
        endcase
		if(out == 4'd0 && code != 8'h45)begin
			valid = 1'b0;
    	end
    	else begin
    		valid = 1'b1;
    	end
     end       

endmodule

6.2 Build a circuit from a simulation waveform

6.2.1 Combinational circuit 1（Sim/circuit1）

module top_module (
    input a,
    input b,
    output q );//

    assign q = a & b; // Fix me

endmodule

6.2.2 Combinational circuit 2（Sim/circuit2）

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

	assign q = ~a & ~b & ~c & ~d | ~a & ~b & c & d | ~a & b & ~c & d | ~a & b & c & ~d | a & b & ~c & ~d | a & b & c & d | a & ~b & ~c & d | a & ~b & c & ~d;		 // 卡诺图

endmodule

6.2.3 Combinational circuit 3（Sim/circuit3）

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

     assign q = b & d | b & c | a & d | a & c; //卡诺图推关系式
    
endmodule

6.2.4 Combinational circuit 5（Sim/circuit5）

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//
 
    assign q = b | c;  //卡诺图推关系式
 
endmodule

6.2.5 Combinational circuit 5（Sim/circuit5）

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );

    always@(*)begin
        case(c)
            0:begin
                q = b;
            end
            1:begin
                q = e;
            end
            2:begin
                q = a;
            end
            3:begin
                q = d;
            end
            default:begin
                q = 4'hf;
            end
        endcase
    end
    
endmodule

6.2.6 Combinational circuit 6（Sim/circuit6）

module top_module (
    input [2:0] a,
    output reg [15:0] q ); 
    
    always@(*)begin
        case(a)
            0:begin
                q = 16'h1232;
            end
            1:begin
                q = 16'haee0;
            end
            2:begin
                q = 16'h27d4;
            end
            3:begin
                q = 16'h5a0e;
            end
            4:begin
                q = 16'h2066;
            end
            5:begin
                q = 16'h64ce;
            end
            6:begin
                q = 16'hc526;
            end
            7:begin
                q = 16'h2f19;
            end
        endcase
    end
 
endmodule

6.2.7 Sequential circuit 7（Sim/circuit7）

module top_module (
    input clk,
    input a,
    output q );
    
    always@(posedge clk)begin
        q <= ~a;	//取反
    end
 
endmodule

6.2.8 Sequential circuit 8（Sim/circuit8）

module top_module (
    input clock,
    input a,
    output p,
    output q );
    
    //p输出的逻辑
    always@(*)begin
        if(clock)begin
        	p = a;
        end
    end
    //q的输出逻辑
    always@(negedge clock)begin
        q <= p;
    end
 
endmodule

6.2.9 Sequential circuit 9（Sim/circuit9）

module top_module (
    input clk,
    input a,
    output [3:0] q );
    
    //置数为4的计数器
    always@(posedge clk)begin
        if(a)begin
            q <= 4'd4;
        end
        else if(q == 4'd6)begin
            q <= 4'd0;
        end
        else begin
            q <= q + 1'b1;
        end
    end
 
endmodule

6.2.10 Sequential circuit 10（Sim/circuit10）

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    //时序逻辑生成state    
    always@(posedge clk)begin
        if(a == b)begin
        	state <= a;
        end
    end
    
    //组合逻辑生成q
    always@(*)begin
        q = a & ~b & ~state | ~a & ~b & state | a & b & state | ~a & b & ~state;
    end
 
endmodule

7 Verification: Writing Testbenches

7.1 Clock（Tb/clock）

module top_module ( );
	
    dut u1_dut(
        .clk(clk	)
    );
    
	initial begin
        clk = 1'b0;
    end
    
    always begin
        #5
        clk = ~clk;
    end

endmodule

7.2 Testbench1（Tb/tb1）

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
 		//0
        A=1'b0;
        B=1'b0;
        
        //10
        #10;
        A = 1'b1;
        B = 1'b0;
        //15
        #5;
        A = 1'b1;
        B = 1'b1;
        
        //20
        #5;
        A = 1'b0;
        B = 1'b1;
        
        //40
        #20;
        A = 1'b0;
		B = 1'b0
    end

endmodule

7.3 AND gate（Tb/and）

module top_module();
    
    reg [1:0] in;
    wire out;
    
    andgate u1_andgate(
        .in		(in		),
        .out	(out	)
	);
    
	initial begin
		in = 2'b00;
    	#10
    	in = 2'b01;
    	#10
    	in = 2'b10;
    	#10
    	in = 2'b11;
	end

endmodule

7.4 Testbench2（Tb/tb2）

module top_module();
    reg clk;
    reg in;
    reg [2:0] s;
    wire out;
    
    q7 u1_q7(
        .clk	(clk	),
        .in     (in     ),
        .s      (s      ),
        .out    (out	)
    );
    
	
    //clk
    initial begin
        clk = 1'b0;
    end
    
    always begin
        #5
        clk = ~clk;
    end

    //in,s
    initial begin
        in = 1'b0;
        s = 3'd2;
        #10;
        in = 1'b0;
        s = 3'd6;
        #10;
        in = 1'b1;
        s = 3'd2;
        #10;
        in = 1'b0;
        s = 3'd7;
        #10;
        in = 1'b1;
        s = 3'd0;
        #30;
        in = 1'b0;
        s = 3'd0;
    end

endmodule

7.5 T flip-flop（Tb/tff）

module top_module ();
    reg clk;
    reg reset;
    reg t;
    wire q;
    
    tff u1_tff(
        .clk	(clk    ),
        .reset	(reset  ),
        .t      (t      ),
        .q      (q      )
    );
    
    //clk
    initial begin
        clk = 1'b0;
    end
    
    always begin
        #5
        clk = ~clk;
    end
    
    //reset
    initial begin
        reset = 1'b0;
        #3;
        reset = 1'b1;
        #10;
        reset = 1'b0;   
    end
    
    always@(posedge clk)begin
        if(reset)begin
            t <= 1'b0;
        end
        else begin
            t <= 1'b1;
        end
    end
 
endmodule