Verilog刷题HDLBits——Cs450/counter 2bc

题目描述

代码

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    parameter SNT=0,WNT=1,WT=2,ST=3;
    reg[1:0] next_st;
    
    always@(*)
        case(state)
            SNT:next_st=train_valid?(train_taken?WNT:SNT):SNT;
            WNT:next_st=train_valid?(train_taken?WT:SNT):WNT;
            WT:next_st=train_valid?(train_taken?ST:WNT):WT;
            ST:next_st=train_valid?(train_taken?ST:WT):ST;
        endcase
    
    always@(posedge clk or posedge areset)
        if(areset)
            state<=WNT;
        else
            state<=next_st;

endmodule

结果