自己初学所写,如有建议希望您不吝啬,欢迎留下答案
Cs450/timer
module top_module(
input clk,
input load,
input [9:0] data,
output tc
);
reg [9:0] counter;
always@(posedge clk) begin
case({load,tc})
2'b00:counter<=counter-1'b1;
2'b01:counter<=1'b0;
2'b10:counter<=data;
default:counter<=data;
endcase
end
assign tc=(counter==10'b0)?1'b1:1'b0;
endmodule
Cs450/counter 2bc
module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output [1:0] state
);
reg [1:0] nstate,pstate;
always@(*) begin
case({train_valid,train_taken})
2'b11: nstate<=(pstate==2'b11)?2'b11:(pstate+1'b1);
2'b10: nstate<=(pstate==2'b00)?2'b00:(pstate-1'b1);
default:nstate<=pstate;
endcase
end
always@(posedge clk or posedge areset)begin
if(areset)
pstate<=2'b01;
else
pstate<=nstate;
end
assign state=pstate;
endmodule