基于FPGA的模计数器设计VHDL开发

链接：https://pan.baidu.com/s/1VF3q6mVPGvpcgx5fQZOkag
提取码：kgse

控制部分的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Ctrl is
	port(
		clk		:in	std_logic;
		reset_n	:in	std_logic;
		
		sel_l	:in	std_logic;
		sel_h	:in	std_logic;
		
		dir		:in	std_logic;
		
		cnt_10_en	:out	std_logic;
		cnt_12_en	:out	std_logic;
		cnt_24_en	:out	std_logic;
		cnt_60_en	:out	std_logic;
		sd_sel		:out	std_logic_vector(1 downto 0);
		
		dir_out		:out	std_logic
		);
end Ctrl;

architecture rtl of Ctrl is

signal sel_r:std_logic_vector(1 downto 0);

signal cnt_10_en_r:std_logic;
signal cnt_12_en_r:std_logic;
signal cnt_24_en_r:std_logic;
signal cnt_60_en_r:std_logic;
signal sd_sel_r:std_logic_vector(1 downto 0);

signal dir_out_r:std_logic;
			
begin
	
	sel_r <= sel_h & sel_l;
	
	process(clk,rese