Verilog 美观备注

module data_gen(
    input                clk           ,  
    input                rst_n         ,  
    input                sd_init_done  ,  
    output               error_flag       
    );

//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg              sd_init_done_d0  ;       
reg              sd_init_done_d1  ;       
reg              wr_busy_d0       ;       
reg              wr_busy_d1       ;
reg    [15:0]    wr_data_t        ;    
reg    [15:0]    rd_comp_data     ;       
reg    [8:0]     rd_right_cnt     ;       

//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
wire             pos_init_done    ;       
wire             neg_wr_busy      ;       

//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign  pos_init_done = (~sd_init_done_d1) & sd_init_done_d0;
assign  neg_wr_busy = wr_busy_d1 & (~wr_busy_d0);
assign  wr_data = (wr_data_t > 16'd0)  ?  (wr_data_t - 1'b1) : 16'd0;
assign  error_flag = (rd_right_cnt == (9'd256))  ?  1'b0 : 1'b1;

//------------------------------------------------------------------------------
//----------- main code --------------------------------------------------------
//------------------------------------------------------------------------------

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        sd_init_done_d0 <= 1'b0;
        sd_init_done_d1 <= 1'b0;
    end
    else begin
        sd_init_done_d0 <= sd_init_done;
        sd_init_done_d1 <= sd_init_done_d0;
    end        
end

endmodule

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