FPGA实现中值滤波（采用shift_ram的ip核）

实现代码

中值滤波模块中还包含着filter_3x3模块和sort模块，而filter_3x3模块中又需要用到shift_ram的ip核模块。

module Median
//========================< 端口 >==========================================
(
input   wire                clk                     ,
input   wire                rst_n                   ,
//input ---------------------------------------------
input   wire                Y_de                    ,
input   wire                Y_hsync                 ,
input   wire                Y_vsync                 ,
input   wire    [15:0]      Y_data                  ,
//output --------------------------------------------
output  wire                median_de               ,
output  wire                median_hsync            ,
output  wire                median_vsync            ,
output  wire    [15:0]      median_data
);
//========================< 信号 >==========================================
//filter_3x3 ----------------------------------------
wire 	  [15:0]     filter_11,filter_12,filter_13    ;
wire 	  [15:0]     filter_21,filter_22,filter_23    ;
wire 	  [15:0]     filter_31,filter_32,filter_33    ;
//median --------------------------------------------
wire    [15:0]              max_data1               ;
wire    [15:0]              mid_data1               ;
wire    [15:0]              min_data1               ;
wire    [15:0]              max_data2               ;
wire    [15:0]              mid_data2               ;
wire    [15:0]              min_data2               ;
wire    [15:0]              max_data3               ;
wire    [15:0]              mid_data3               ;
wire    [15:0]              min_data3               ;
wire    [15:0]              max_min_data            ;
wire    [15:0]              mid_mid_data            ;
wire    [15:0]              min_max_data            ;
//同步 ----------------------------------------------
reg     [ 3:0]              Y_de_r                  ;
reg     [ 3:0]              Y_hsync_r               ;
reg     [ 3:0]              Y_vsync_r               ;
//==========================================================================
//==    3x3矩阵模块例化，耗费1clk
//==========================================================================
filter_3x3 filter_3x3_inst(
    .clk      (clk      ),
    .rst_n    (rst_n    ),
	.gray_de  (Y_de     ),	 
    .iData    (Y_data   ),

    .oData_11 (filter_11), .oData_12 (filter_12), .oData_13 (filter_13),
    .oData_21 (filter_21), .oData_22 (filter_22), .oData_23 (filter_23),
    .oData_31 (filter_31), .oData_32 (filter_32), .oData_33 (filter_33)
);
//==========================================================================
//==    中值滤波，耗费3clk
//==========================================================================
//每行像素降序排列，clk1
//---------------------------------------------------
//第1行
sort u1
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (filter_11              ), 
    .data2                  (filter_12              ), 
    .data3                  (filter_13              ),
    .max_data               (max_data1              ),
    .mid_data               (mid_data1              ),
    .min_data               (min_data1              )
);

//第2行
sort u2
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (filter_21              ),
    .data2                  (filter_22              ),
    .data3                  (filter_23              ),
    .max_data               (max_data2              ),
    .mid_data               (mid_data2              ),
    .min_data               (min_data2              )
);

//第3行
sort u3
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (filter_31              ),
    .data2                  (filter_32              ),
    .data3                  (filter_33              ),
    .max_data               (max_data3              ),
    .mid_data               (mid_data3              ),
    .min_data               (min_data3              )
);

//三行的最小值取最大值
//三行的中间值取中间值
//三行的最大值取最小值，clk2
//---------------------------------------------------
//min-max
sort u4
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (min_data1              ),
    .data2                  (min_data2              ),
    .data3                  (min_data3              ),
    .max_data               (min_max_data           ),
    .mid_data               (                       ),
    .min_data               (                       )
);

//mid-mid
sort u5
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (mid_data1              ),
    .data2                  (mid_data2              ),
    .data3                  (mid_data3              ),
    .max_data               (                       ),
    .mid_data               (mid_mid_data           ),
    .min_data               (                       )
);

//max-min
sort u6
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (max_data1              ), 
    .data2                  (max_data2              ), 
    .data3                  (max_data3              ),
    .max_data               (                       ),
    .mid_data               (                       ),
    .min_data               (max_min_data           )
);

//前面的三个值再取中间值，clk3
//---------------------------------------------------
sort u7
(
    .clk                    (clk                    ),
    .rst_n                  (rst_n                  ),
    .data1                  (max_min_data           ),
    .data2                  (mid_mid_data           ), 
    .data3                  (min_max_data           ),
    .max_data               (                       ),
    .mid_data               (median_data            ),
    .min_data               (                       )
);
//==========================================================================
//==    信号同步（打四拍）
//==========================================================================
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        Y_de_r    <= 4'b0;
        Y_hsync_r <= 4'b0;
        Y_vsync_r <= 4'b0;
    end
    else begin  
        Y_de_r    <= {Y_de_r[2:0],    Y_de};
        Y_hsync_r <= {Y_hsync_r[2:0], Y_hsync};
        Y_vsync_r <= {Y_vsync_r[2:0], Y_vsync};
    end
end

assign median_de    = Y_de_r[3];
assign median_hsync = Y_hsync_r[3];
assign median_vsync = Y_vsync_r[3];
    


endmodule

 

使能信号和行场同步信号，均打了四拍。 

IP核设置 

中值滤波结果

输入图片：

中值滤波后的输出图片：