PACKAGE_PIN

PACKAGE_PIN定义了逻辑中顶级端口的特定分配或放置
设计设备上的物理封装引脚。
建议：要将I/O端口分配给设备包上的物理引脚，请使用package_PIN
财产而不是LOCS。使用LOC属性将逻辑单元分配给目标上的设备资源
Xilinx FPGA。
架构支持
所有架构。
适用对象
•端口（get_Ports）
°任何顶级端口
价值观
包装引脚名称

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the port declaration:

(* PACKAGE_PIN = "pin_name" *)

Verilog Syntax Example

// Designates port CLK to be placed on pin B26

(* PACKAGE_PIN = "B26" *) input CLK;

VHDL Syntax

Declare the VHDL attribute as follows:

attribute PACKAGE_PIN : string;

Specify the VHDL attribute as follows:

attribute PACKAGE_PIN of port_name : signal is "pin_name";

VHDL Syntax Example

-- Designates CLK to be placed on pin B26

attribute PACKAGE_PIN of CLK : signal is "B26";

XDC Syntax

set_property PACKAGE_PIN pin_name [get_ports port_name]

XDC Syntax Example

# Designates CLK to be placed on pin B26

set_property PACKAGE_PIN B26 [get_ports CLK]