verilog中各种逻辑门 非门not assign y = ~a;//非门 与门and assign y = a & b;//与门 或门or assign y = a | b;//或门 异或门xor assign y = a ^ b;//异或门 与非门nand assign out = ~(a&b); 或非门nor assign out = ~(a|b); 同或门(异或非门)xnor assign out = ~(a^b); 符号示意图符号示意图: