//异步复位存在的隐患
module top(
input clk ,
input rst_n ,
input a ,
output reg b ,
output reg b ,
);
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
b <= 1'b0;
else
b <= a;
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
c <= 1'b0;
else
c <= b;
end
endmodule