FPGA-呼吸灯

• 波形绘制

•  RTL代码

  module breath_led
  #(
  	parameter CNT_1S = 10'd999,
  	parameter CNT_1MS = 10'd999,
  	parameter CNT_1US = 6'd49
  )
  (
  	input wire sys_clk,
  	input wire sys_rst_n,
  	
  	output reg led_out
  );
  
  reg [9:0] cnt_ls;
  reg [9:0] cnt_1ms;
  reg [5:0] cnt_1us;
  reg cnt_en;
  
  always@(posedge sys_clk or negedge sys_rst_n)
  	if(!sys_rst_n)
  		cnt_1us <= 6'd0;
  	else if(cnt_1us == CNT_1US)
  		cnt_1us <= 6'd0;
  	else
  		cnt_1us <= cnt_1us + 6'd1;
  		
  always@(posedge sys_clk or negedge sys_rst_n)
  	if(!sys_rst_n)
  		cnt_1ms <= 10'd0;
  	else if(cnt_1ms == CNT_1MS && (cnt_1us == CNT_1US))
  		cnt_1ms <= 10'd0;
  	else if(cnt_1us == CNT_1US)
  		cnt_1ms <= cnt_1ms + 10'd1;
  	else 
  		cnt_1ms <= cnt_1ms;
  
  always@(posedge sys_clk or negedge sys_rst_n)
  	if(!sys_rst_n)
  		cnt_ls <= 10'd0;
  	else if((cnt_ls == CNT_1S) && (cnt_1ms == CNT_1MS) && (cnt_1us == CNT_1US))
  		cnt_ls <= 10'd0;
  	else if((cnt_1us == CNT_1US) && (cnt_1ms == CNT_1MS))
  		cnt_ls <= cnt_ls + 10'd1;
  	else	
  		cnt_ls <= cnt_ls;
  
  always@(posedge sys_clk or negedge sys_rst_n)
  	if(!sys_rst_n)
  		cnt_en <= 1'b0;
  	else if((cnt_ls == CNT_1S) && (cnt_1us == CNT_1US) && (cnt_1ms == CNT_1MS))
  		cnt_en <= ~cnt_en;
  	else
  		cnt_en <= cnt_en;
  		
  always@(posedge sys_clk or negedge sys_rst_n)
  	if(!sys_rst_n)
  		led_out <= 1'b1;
  	else if(((cnt_en == 1'b0) && (cnt_1ms <= cnt_ls)) || ((cnt_en == 1'b1) && (cnt_1ms > cnt_ls)))
  		led_out <= 1'b0;
  	else	
  		led_out <= 1'b1;
  		
  endmodule

• 仿真代码

  `timescale 1ns/1ns
  
  module breath_led_tb();
  
  
  reg sys_clk;
  reg sys_rst_n;
  
  wire led_out;
  
  initial begin
  	sys_clk = 1'b1;
  	sys_rst_n <= 1'b0;
  	#20
  	sys_rst_n <= 1'b1;
  end
  
  always #10 sys_clk = ~sys_clk;
  
  module breath_led
  #(
  	.CNT_1S(6'd4),
  	.CNT_1MS(10'd9),
  	.CNT_1US(10'd9)
  )
  breath_red_inst
  (
  	.sys_clk(sys_clk),
  	.sys_rst_n(sys_rst_n),
  	.led_out(led_out)
  );
  endmodule

• 仿真结果
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• 运行效果