（奇哥状态机）流水线-乒乓操作

项目框图

*

使用奇哥状态机完成最关键

//状态机跳转
    always@(posedge clk_50m,posedge rst_n)
    begin
        if(~rst_n)
            r_st_current <= IDLE;
        else
            r_st_current <= r_st_next;
    end

//跳转条件
    always@(*)
    begin
        case (r_st_current)
                IDLE          : r_st_next = (data_en == 1'b1) ? WRAM1: IDLE;
                WRAM1         : r_st_next = (ram1_wr_addr == 7'd99) ? WRAM2_RRAM1:WRAM1;
                WRAM2_RRAM1   :r_st_next =(ram2_wr_addr == 7'd99) ? WRAM1_RRAM2 :WRAM2_RRAM1;
                WRAM1_RRAM2   : r_st_next =(ram1_wr_addr == 7'd99) ? WRAM2_RRAM1:WRAM1_RRAM2;
            default : r_st_next=IDLE ;
        endcase

    end

    //状态机计数
 always@(posedge clk_50m,posedge rst_n)
begin
    if(rst_n)
        r_st_cnt <= 'd0;
    else if(r_st_current != r_st_next)
        r_st_cnt <= 'd0;
    else 
        r_st_cnt <= r_st_cnt + 1;
end

//状态机的驱动逻辑
    always@(*)
    case(r_st_current)
        IDLE:
            begin
                ram1_wr_en  =  1'b0;
                ram2_wr_en  =  1'b0;
            end
        WRAM1:
            begin
                ram1_wr_en  =  1'b1;
                ram2_wr_en  =  1'b0;
            end
        WRAM2_RRAM1:
            begin
                ram1_wr_en  =  1'b0;
                ram2_wr_en  =  1'b1;
            end
        WRAM1_RRAM2:
            begin
                ram1_wr_en  =  1'b1;
                ram2_wr_en  =  1'b0;
            end
        default:;
    endcase

其他就是RAM的读写操作。最后实现效果图

写入的数据

读出的数据

状态机跳转正常计数一直为0，输出正常