【HDLBits刷题】HDLBits_Verilog学习笔记Ⅲ——Circuit_Combinational Logic_Multiplexers

1.Mux2to1

module top_module(
    input a, b, sel,
    output out );
    assign out=(sel)?b:a;
endmodule

 2.Mux2to1v

module top_module(
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    assign out=(sel)?b:a;
endmodule

3.Mux9to1v

module top_module(
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always @(*) begin
        case (sel)
            0: out = a;
            1: out = b;
            2: out = c;
            3: out = d;
            4: out = e;
            5: out = f;            
            6: out = g;
            7: out = h;
            8: out = i;
            default : out = 16'b1111111111111111;
        endcase
    end
endmodule

4. Mux256to1

module top_module(
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

 5.Mux256to1v

module top_module(
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};

//注意这里不可以写成out[3:0] = in[(sel*4+3):sel*4];
endmodule