HDLBits学习笔记（81~98)

HDLBits学习笔记（81~98)

学习阶段：有问题发873727286@qq.com大家一起讨论。

题目81 Dff

题干：D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire.Create a single D flip-flop.

题目大意：使用always语句制作一个D触发器。

题目分析：当clk为高电平时，数据由d->q。

答案：

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always@(posedge clk)begin
        q <= d; 
    end
endmodule

题目82 Dff8

题干：Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.

题目大意：创建8个D触发器，所有的 触发器都在CLK高电平时被触发。

题目分析：当clk为上升沿时，数据由d[7:0]->q[7:0]。

答案：

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
	always@(posedge clk)begin
        q <= d; 
    end
endmodule

题目83 Dff8r

题干：Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.

题目大意：相较于上一个题，多了一个高电平的同步复位。

题目分析：当clk为上升沿时，数据由d[7:0]->q[7:0]。当reset为高电平时输出为0。

答案：

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)begin
        if(reset)
            q <= 8'd0;
        else
            q <= d;
	end
endmodule

题目84 Dff8p

题干：Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

题目大意：相较于上一个题，高电平的同步复位的值为0x34。并且时clk低电平触发。

题目分析：当clk为低电平时，数据由d[7:0]->q[7:0]。当reset为高电平时输出为0x34。

答案：

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk)begin
        if(reset)
            q <= 8'h34;
        else
            q <= d;
	end
endmodule

题目85 Dff8ar

题干：Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

题目大意：高电平的异步复位的值为0x34。并且时clk高电平触发。

题目分析：异步复位，areset也要在敏感时间表中。

答案：

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset)begin
        if(areset)
            q <= 8'd0;
        else
            q <= d;
	end
endmodule

题目86 Dff16e

题干：Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.

题目大意：创建一个16位的D触发器，byteena[1]控制高八位，byteena[0]控制低八位，resetn是同步复位信号，低电平有效

题目分析：通过在always中增加对byteena的判断控制D触发器高八位和低八位的使能，resetn是一个低电平有效的同步复位信号。

答案：

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)begin
        if(!resetn)
            q <= 16'b0;
        else case(byteena)
            2'd0:q <= q;
            2'd1:q[7:0] <= d[7:0];
            2'd2:q[15:8] <= d[15:8];
            2'd3:q[15:0] <= d[15:0];
        endcase
    end
endmodule

题目87 Exams/m2014 q4a

题干：Implement the following circuit:

题目大意：按图创建一个锁存器。

题目分析：锁存器是电平敏感（非边缘敏感）电路，因此在“always”块中，它们使用电平敏感灵敏度列表。但仍是时序结构，应该使用非阻塞赋值。

答案：

module top_module (
    input d, 
    input ena,
    output q);
	always@(*) begin
        if (ena)
            q <= d;
    end
endmodule

题目88 Exams/m2014 q4b

题干：Implement the following circuit:

题目大意：实现如图所示电路。

题目分析：异步复位的D触发器。

答案：

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always@(posedge clk or posedge ar)begin
        if(ar)
            q <= 1'b0;
        else
            q <= d;
    end
endmodule

题目89 Exams/m2014 q4c

题干：Implement the following circuit:

题目大意：实现如图所示电路。

题目分析：同步复位的D触发器。

答案：

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
	always@(posedge clk) begin
        if (r)
            q<=0;
        else
            q<=d;
    end
endmodule

题目90 Exams/m2014 q4d

题干：Implement the following circuit:

题目大意：实现如图所示电路。

题目分析：D触发器的输入经过一个异或门。

答案：

module top_module (
    input clk,
    input in, 
    output out);
	wire d;
    assign d = in^out;
    always@(posedge clk)begin
       out <= d;
    end
endmodule

题目91 Mt2015 muxdff

题干：Consider the sequential circuit below:
Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

题目大意：实现如图所示电路的其中一部分电路（数据选择器和D触发器的组合）。

题目分析：多路数据选择器和D触发器的组合。

答案：

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    wire d;
    always@(posedge clk)
        Q<=d;
    assign d=(L)?r_in:q_in;
endmodule

题目92 Exams/2014 q4a

题干：Consider the n-bit shift register circuit shown below:

Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

题目大意：实现如图所示位移寄存器电路的其中一部分电路（数据选择器和D触发器的组合）。

题目分析：多路数据选择器和D触发器的组合。

答案：

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
	wire d1,d2;
    assign d1 = (E)?(w):(Q);
    assign d2 = (L)?(R):(d1);
    always@(posedge clk)begin
        Q <= d2;
    end
endmodule

题目93 Exams/ece241 2014 q4

题干：Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.
Build this circuit.

题目大意：假设D触发器初始化为0，构建图示电路。

题目分析：D触发器和门电路组合，可以用D触发器模块的实例化实现。

答案：

module top_module (
    input clk,
    input x,
    output z
); 
    wire d1,d2,d3;
    reg q1=0,q2=0,q3=0;
    assign d1 = x^q1;
    assign d2 = x&~q2;
    assign d3 = x|~q3;
    assign z = ~(q1|q2|q3);
    DFF1 instance1(d1,clk,q1);
    DFF1 instance2(d2,clk,q2);
    DFF1 instance3(d3,clk,q3);
endmodule

module DFF1 (
	input wire d,
    input wire clk,   
    output reg q
);
    always@(posedge clk)begin
        q <= d;
    end
endmodule

题目94 Exams/ece241 2013 q7

题干：A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

J	K	Q
0	0	Qold
0	1	0
1	0	1
1	1	~Qold

题目大意：只使用一个D触发器和逻辑门实现上述的JK触发器。

题目分析：根据JK触发器的特征方程，即可写出答案。

$$Qn+1=J{Q}^{\prime }+K^{\prime }Q,.$$
答案：

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
	wire q1, q2, q3;
    assign q1 = j&(~Q);
    assign q2 = ~k&Q;
    assign q3 = q1 | q2;
    always@(posedge clk)
        Q <= q3;
endmodule

题目95 Edgedetect

题干：For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

题目大意：八位输入中发生0–>1跳变，对应的输出位要位拉高。

题目分析：可以先对前一个输入取反，在和后一个输入相与， 注意输出延后一个时钟周期。

答案：

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] in1;
    always@(posedge clk)begin
        in1 <= in; //落后一个时钟周期
        pedge <= ~(in1)&in;
    end
endmodule

题目96 Edgedetect2

题干：For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

题目大意：八位输入中发生0–>1跳变或者1–>0跳变，对应的输出位要位拉高。

题目分析：可以使用异或解决， 注意输出延后一个时钟周期。

答案：

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
	    reg [7:0] in1;
    always@(posedge clk)begin
        in1 <= in;
        pedge <= in1^in;
    end
endmodule

题目97 Edgecapture

题干：For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).
Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.
In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

题目大意：记录从1–>0跳变，而且输出中的1会保持，当reset置高(同步复位)才会把输出的1释放。

题目分析：可以先对后一个输入取反，在和前一个输入相与， 注意输出延后一个时钟周期。

答案：

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] in1;
    always@(posedge clk)begin
        in1 <= in ;
        if(reset)
            out <= 32'b0;
        else
            out <= (~(in)&in1)|out;
    end
endmodule

题目98 Dualedge

题干：You’re familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don’t have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.
Build a circuit that functionally behaves like a dual-edge triggered flip-flop

题目大意：构建一个双边时钟触发的D触发器。此时只落后半个时钟周期。

答案：

module top_module (
    input clk,
    input d,
    output q
);
    reg q_p,q_n;
    always@(posedge clk)begin
        q_p <= d ^ q_n;
    end
    always@(negedge clk)begin
        q_n <= d ^ q_p;
    end  
    assign q = q_p ^ q_n; //此时只落后半个时钟周期
    
endmodule