HDLbits--Exams/ece241 2013 q8

 四个状态

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter idel=0,b1=1,b2=2,b3=3;
    reg [1:0] state, next_state;
    
    always@(*)
        begin
            case(state)
                idel:
                    next_state<=x?b1:idel;
                b1:
                    next_state<=x?b1:b2;
                b2:
                    next_state<=x?b3:idel;
                b3:
                    next_state<=x?b1:b2;
            endcase
        end
    
    always@(posedge clk,negedge aresetn)
        begin
            if(!aresetn)
                state<=idel;
            else
                state<=next_state;
        end
    
    assign z=next_state==b3;

endmodule

 三个状态：

把检测第三bit的状态省去，只有三个状态，其中idle是检测到首bit为0，b1检测到首bit为1，b2是检测到10状态，当状态在b2时，再接收到1说明是101，也是下一个序列的开头为1的状态；当收到0时说明是开头为0的状态。

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter idel=0,b1=1,b2=2;
    reg [1:0] state, next_state;
    
    always@(*)
        begin
            case(state)
                idel:
                    next_state<=x?b1:idel;
                b1:
                    next_state<=x?b1:b2;
                b2:
                    next_state<=x?b1:idel;
                default:next_state<=idel;
            endcase
        end
    
    always@(posedge clk,negedge aresetn)
        begin
            if(!aresetn)
                state<=idel;
            else
                state<=next_state;
        end
    
    assign z=state==b2&&x==1;

endmodule