Q8:Design a Mealy FSM（Exams/ece241 2013 q8）

题目
Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter S0 = 2'd0, S1 = 2'd1, S2 = 2'd3;
    reg [1:0]	current_state;
    reg [1:0]	next_state;
    
    always@(posedge clk or negedge aresetn)begin
        if(aresetn == 1'b0)begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            S0:begin
                next_state = x ? S1 : S0;
            end
            S1:begin
                next_state = x ? S1 : S2;
            end
            S2:begin
                next_state = x ? S1 : S0;
            end
            default:begin
                next_state = S0;
            end
        endcase
    end
    
    assign z = x & (&current_state);
    
endmodule