Verilog刷题HDLBits——Exams/ece241 2013 q8

题目描述

Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

代码

// 解法一：4状态
module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter idle=0,b1=1,b2=2,b3=3;
    reg[1:0] state,next_state;
    
    always@(*)
        case(state)
            idle:next_state=x?b1:idle;
            b1:	 next_state=x?b1:b2;
            b2:	 next_state=x?b3:idle;
            b3:	 next_state=x?b1:b2;
        endcase
    
    always@(posedge clk or negedge aresetn)
        if(!aresetn)
            state<=idle;
    	else
            state<=next_state;
    
    assign z = (state==b2)&&(x==1);

endmodule

// 解法二：3状态
module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter idle=0,b1=1,b2=2;
    reg[1:0] state,next_state;
    
    always@(*)
        case(state)
            idle:next_state=x?b1:idle;
            b1:	 next_state=x?b1:b2;
            b2:	 next_state=x?b1:idle;
        endcase
    
    always@(posedge clk or negedge aresetn)
        if(!aresetn)
            state<=idle;
    	else
            state<=next_state;
    
    assign z = (state==b2)&&(x==1);

endmodule

// 参考解法
module top_module (
	input clk,
	input aresetn,
	input x,
	output reg z
);

	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	parameter S=0, S1=1, S10=2;
	reg[1:0] state, next;		// Make sure state and next are big enough to hold the state encodings.
	
	
	
	// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.			
	always@(posedge clk, negedge aresetn)
		if (!aresetn)
			state <= S;
		else
			state <= next;
			
	

    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
	always@(*) begin
		case (state)
			S: next = x ? S1 : S;
			S1: next = x ? S1 : S10;
			S10: next = x ? S1 : S;
			default: next = 'x;
		endcase
	end
	
	
	
	// Combinational output logic. I used a combinational always block.
	// In a Mealy state machine, the output depends on the current state *and*
	// the inputs.
	always@(*) begin
		case (state)
			S: z = 0;
			S1: z = 0;
			S10: z = x;		// This is a Mealy state machine: The output can depend (combinational) on the input.
			default: z = 1'bx;
		endcase
	end
	
endmodule

结果