hdlbits count clock 新手解答

题干：

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

Module Declaration

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

解答：

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    wire en1,en2;
    cnt ss1 (clk, reset, ena, ss);
    cnt mm1 (clk, reset, en1, mm);
    cnt1 hh1 (clk, reset, en2, hh);
    assign en1 = (ss==8'b01011001)?1:0;
    assign en2 = (mm==8'b01011001&&ss==8'b01011001)?1:0;
    always @(posedge clk)begin
        if(reset)begin
            pm<=0;
        end
        else if(hh==8'b00010001&&mm==8'b01011001&&ss==8'b01011001)begin
            pm<=!pm;
        end
        else
            pm<=pm;
    end
            
endmodule

module cnt (
    input clk,
    input reset,
    input en ,
    output [7:0] out);
    reg[7:0] q,q1;
    always@(posedge clk)begin
        if(reset)begin
            q<=0;
        end
        else if(en) begin
            if(q==59)
                q<=0;
            else
                 q<=q+1;
        end
else
    q<=q;
    end
    bcd bb (q, q1);
    assign out = q1;
    
endmodule

module cnt1 (
    input clk,
    input reset,
    input en ,
    output [7:0] out);
    reg [7:0] q,q1;
    always@(posedge clk)begin
        if(reset)begin
            q<=12;
        end
        else if(en) begin
            if(q==12)
                q<=1;
            else
                 q<=q+1;
        end
else
    q<=q;
    end  
        bcd aa (q, q1);
        assign out = q1;
endmodule

module bcd (
    input [7:0] in,
    output [7:0] out);
    reg [3:0] ten, one;
    integer i;
    always@(*)begin
        one=0;
        ten=0;
        for(i=7;i>=0;i=i-1)begin
            if(one>=5) one=one+3;
            if(ten>=5) ten=ten+3;
            ten={ten[2:0],one[3]};
            one={one[2:0],in[i]};
           end
      end
                 assign out = {ten,one};
endmodule

思路：

用到0-59计数器和1-12计数器；

使用bin2bcd让计数器输出为bcd码；

pm每当hh11-12时翻转一次。

欢迎指正！谢谢！