Verilog刷题笔记51

题目：
Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don’t-care).

解题：

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	parameter s0=0,s1=1,s2=2,s3=3;
    reg [1:0]state,next_state;
    reg [23:0]data;
    always@(posedge clk)begin
        if(reset)
            state=s0;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            s0:next_state=(in[3]==1)?s1:s0;
            s1:next_state=s2;
            s2:next_state=s3;
            s3:next_state=(in[3]==1)?s1:s0;
            default:next_state=s0;
        endcase
    end
    assign done=(state==s3)?1:0;
    always@(posedge clk)begin
        if(reset)
            data=24'd0;
        else begin
            data[23:16]=data[15:8];
            data[15:8]=data[7:0];
            data[7:0]=in;
        end
    end
    assign out_bytes=(done)?data:24'd0;
            
    // FSM from fsm_ps2
	
    // New: Datapath to store incoming bytes.

endmodule

结果正确：

知识点：
在基础的状态机上，引入一个data来存储之前的数据。