hdlbits Exams/ece241 2014 q5b

题干：

The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding.

Module Declaration

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

解答：

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg [1:0] state , next_state ;
    parameter [1:0] a=2'b01, b=2'b10;
    always@(*)begin
        case(state)
            a:begin
                if(x) begin next_state = b; z=1; end
                else begin next_state = a; z=0; end
            end
            b:begin
                if(x) begin next_state = b; z=0; end
                else begin next_state = b; z=1; end
            end
            //default:
        endcase
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset) state <= a;
        else state <= next_state;
    end
    
                    
endmodule