VHDL四位比较器

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;


ENTITY Vhdl1 IS
    PORT (a0,b0,a1,b1,a2,b2,a3,b3: in STD_LOGIC ;
       E      : OUT STD_LOGIC ;
 L      : OUT STD_LOGIC ;
 G      : OUT STD_LOGIC ) ;

END Vhdl1 ;
ARCHITECTURE LogicFunc of Vhdl1 is
BEGIN
    E <= (a3 XNOR b3)AND (a2 XNOR b2) AND (a1 XNOR b1) AND (a0 XNOR b0) ;
     
    
 G <= (NOT b3 AND a3) OR 
 ((a3 XNOR b3 ) AND (NOT b2)AND a2)OR
 ((a3 XNOR b3 )AND (a2 XNOR b2)AND(NOT b1)AND a1)OR
 ((a3 XNOR b3)AND (a2 XNOR b2)AND(a1 XNOR b1)AND (NOT b0)AND a0)
 
 ;
 L <= ((a3 XNOR b3)AND (a2 XNOR b2) AND (a1 XNOR b1) AND (a0 XNOR b0))NOR
 ((NOT b3 AND a3) OR 
 ((a3 XNOR b3 ) AND (NOT b2)AND a2)OR
 ((a3 XNOR b3 )AND (a2 XNOR b2)AND(NOT b1)AND a1)OR
 ((a3 XNOR b3)AND (a2 XNOR b2)AND(a1 XNOR b1)AND (NOT b0)AND a0));
 

END LogicFunc ;