Allegro DFM Ravel Rule检查工具介绍

Allegro DFM Ravel Rule检查工具介绍

Allegro任何一个版本都支持DFM Ravel Rule检查，即便是166的版本
打开后的界面如下所示

可以检查项目
测试点，阻焊，走线，丝印，过孔，milling，装配，outline相关的DFM检查
可以让违反规则的设计处以DRC的形式报出来
避免加工问题
首先介绍如何打开这个工具

1. 软件在默认的情况下是无法打开这个工具，需要添加一个用户环境变量
   如下图
   

DFM_RAV_PATH
D:\Cadence\SPB_16.6\share\pcb\dfm_ravel
这是软件安装路径
2. 切换was performance editor

3. 打开DFM RAVEL界面
   

工具就启动成功了

工具同时支持调入一个设置好的规则，点击Rule调入规则
Clear CM可以清除已经设置好的规则

This section is describe what the function allegro have ,helpfully could let user know more about allegro
Allegro Design and Analysis includes design authoring
PCB layout and Library and Design Data Management
With. It can ensure the end-to-end design of PCB with high quality and efficiency
Realize smooth data transfer between tools, shorten PCB design cycle, and shorten product
Market time

1. Design authoring
   Provide a flexible logic constraint driven flow, management design rules, network hierarchy,
   Bus and differential pair.
   1.1.1 Main features and functions
   Through hierarchical and design “derivation” function, improve the original of complex design
   Map editing efficiency.
   Powerful CIS helps