HDLBits练习——Exams/ece241 2014 q7a

Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1
Enable Set high for the counter to run
Clk Positive edge-triggered clock input
Q[3:0] The output of the counter
c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
logic gates
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter’s enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

---

前言

三个输入，包括一个时钟clk，一个高电平有效的同步置位信号reset，一个使能信号enable；四个输出，包括一个输出信号Q，以及三个检测信号c_enable、c_load 和 c_d。

代码

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
);    
    assign c_enable=enable;
    assign c_load=(reset|(Q==4'd12&enable))?1'b1:1'b0;
    assign c_d=c_load?4'b1:Q;
    count4 instance1(clk,c_enable,c_load,c_d,Q);
endmodule

总结

提供了模块count4，可以直接例化，但是本题主要考虑对于四位计数器的理解，时钟和使能信号都很好理解，但是对于load信号，其代表的是重新加载，即回到初始值，那么就存在两种情况，一是有效置位reset==1’b1，二是计数循环结束并可以开始下一循环，即Q值达到4’d12并且使能信号enable为1’b1，两种情况为或关系；对于d信号而言，其在load信号有效时值为4‘d1，其余情况为任意值即可。