zynq——AXI_lite入门

AXI lite接口一、基础AXI4包括了1、AXI lite（一般用于传输少数据的ip通信或小批量数据）2、AXI full（高级知识）3、AXI stream（以数据流的形式发送数据，与1，2不同，它没有地址，视频常用）。

Axi-lite 1、柴油机和复位：ACLK（同步时钟）和aresetn（同步，低数据源有效复位）2、地址（1）写地址：地址写（aw）AWADDR（2）读地址：读地址（ ar ） ARADDR (1 byte <=> 1地址) 3、//写数据（w，wdata）：【字节到机】 WSTRB（从屏蔽，1：有效）！[插入插入图片描述（https:// /img-blog.csdnimg.cn/5b138b6fa4b9429fae1c5b59832c3182.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dpbmR5c2t5MHYw,size_16,color_FFFFFF,t_70#pic_center）读数据（R，RDATA）：【从机到主机】 RRESP【1:0】（00：ok 01：不存在 10：slave error 11：decode error） 写响应（B）：BVALID [slave -> master] BREADY[m->s] BRESP[1:0]

4、招呼信号地址招呼：（1）写：AWVALID AWREADY（2）读：ARVALID ARREADY 发往从机的请求接收一般情况是主机将AWVALID（请求）和AWADDR（写）一起损坏从机，从机准备好后就反馈AWREADY给主机。AWVALID和AWREADY先后是不分的，只要同时为1，则传输发生。

数据招手： （1）写数据： wvalid【主机到从机】 wready【从机到主机】 （2）读数据：rvalid【从机到主机】 rready【主机到从机】

二、写一个AXI_lite从机

module axi_lite_controllor
#
(
	parameter AXI_ADDRESS_WIDTH = 5
)
(	
	//clock and reset
	input aclk,
	input rst_n,
	
	//write address channel
	input [AXI_ADDRESS_WIDTH-1:0] axi_awaddr,
	input axi_awvalid,
	output axi_awready,
	
	//read address channel
	input [AXI_ADDRESS_WIDTH-1:0] axi_araddr,
	output axi_arready,
	input axi_arvalid,
	
	//write data channel
	input axi_wvalid,
	output axi_wready,
	input [31:0] axi_wdata,
	
	//read data channel
	output axi_rvalid,
	input axi_rready,
	output [31:0] axi_rdata,
	
	//write respone channel
	output axi_bvaild,
	input  axi_bready,

	//设计个寄存器
	output [31:0] reg1,
	output [31:0] reg2
);

//register table
//| ADDRESS | NAME | FUNCTION |
//| 0X000	| REG1 | 		  |
//|	0X004	| REG2 | 		  |

reg [31:0] reg1_reg;
reg [31:0] reg2_reg;

assign reg1 = reg1_reg;
assign reg2 = reg2_reg;

//AXI WRITE ADDRESS CHANNEL
always @(posedge aclk or negedge rst_n)
	if(!rst_n)
		axi_awready <= 1'b0;
	else
	begin
		if(axi_awvalid)
			axi_awready <= 'b1;
		else
			axi_awready <= 'b0;
	end		

reg [AXI_ADDRESS_WIDTH-1:0] axi_awaddr_buffer; //register for address need to write

always @(posedge aclk or negedge rst_n)
	if(!rst_n)
		axi_awaddr_buffer <= 'b0;
	else
		if(axi_awvalid &axi_awready)
			axi_awaddr_buffer <= axi_awaddr;

	
//AXI WRITE data CHANNEL
always @(posedge aclk or negedge rst_n)
	if(!rst_n)
		axi_wready <= 1'b0;
	else
	begin
		if(axi_wvalid)
			axi_wready <= 'b1;
		else
			axi_wready <= 'b0;
	end	

//response request
reg axi_need_resp;//A write operation,need respone

always @(posedge aclk or negedge rst_n)
	if(!rst_n)
		axi_need_resp <= 'b0;

	else
		begin
			if(axi_wvalid && axi_ready)
				axi_need_resp <= 'b1;
			else
				axi_need_resp <= 'b0;
		end


//address selection
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr;  // the real address need to begin writen
always @(*)
	if(axi_wvalid && axi_wready && axi_awvalid && axi_awready)
		axi_waadr <= axi_awaddr;//the address is now available on the interface
	else
		axi_waadr <= axi_awaddr_buffer;// the address is assigned in previous command


//AXI write respone section
always @(posedge aclk or negedge rst_n)
	if(!rst_n)
		axi_bvaild <='b0 ;// 否则		开始if ( axi_need_resp ) 				
		axi_bvaild <= 'b1 ; // 当需要响应if ( axi_bvaild && axi_bready ) 				
		axi_bvaild <= 'b0 ; //当收到响应时		结束//AXI 读地址通道endmodule ```
	//（未完整，有空我再补齐吧（狗头））