前言
本人没有找到专门刷VHDL的网站，如果有请告知，本人不胜感激
1. VHDL转Verilog：X-HDL
参考：https://www.bmabk.com/index.php/post/73693.html
2. HDLBits
网站：https://hdlbits.01xz.net/wiki/Problem_sets#Getting_Started
以Wire为例：
本人写的vhdl代码如下：(当然下面的vhdl是有语法问题的，毕竟in和out都是关键字，但是X-HDL生成的Verilog代码通过了测试=_=!，所以似乎就可以这样刷VHDL了)
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(in : in std_logic;
out : out std_logic);
end top_module;
architecture RTL of top_module is
begin
out <= in;
end RTL;
利用X-HDL生成的verilog如下：
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 5 2024 21:41:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, out);
input in;
output out;
assign out = in;
endmodule
3 刷题
3. 1 刷题一： Combinational Logic Basic Gates
3.1.1 Wire
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(in : in std_logic;
out : out std_logic);
end top_module;
architecture rtl of top_module is
begin
out <= in;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 5 2024 21:41:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, out);
input in;
output out;
assign out = in;
endmodule
3.1.2 GND
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
out: out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= 0;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 10:42:52
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(out);
output out;
assign out = 0;
endmodule
3.1.3 NOR
感觉网站上画的图不是异或门（此处存疑）
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
in1 : in std_logic;
in2 : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= in1 nor in2;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 10:48:11
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in1, in2, out);
input in1;
input in2;
output out;
assign out = ~(in1 | in2);
endmodule
3.1.4 Another gate
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
in1,in2 : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= in1 and (not in2);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 10:50:54
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in1, in2, out);
input in1;
input in2;
output out;
assign out = in1 & ((~in2));
endmodule
3.1.5 Two gates
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port (
in1, in2, in3 : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= (in1 xnor in2) xor in3;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:21:34
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in1, in2, in3, out);
input in1;
input in2;
input in3;
output out;
assign out = (in1 ~^ in2) ^ in3;
endmodule
3.1.6 More logic gates
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b : in std_logic;
out_and,
out_or ,
out_xor,
out_nand,
out_nor,
out_xnor,
out_anotb : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out_and <= a and b;
out_or <= a or b;
out_xor <= a xor b;
out_nand <= a nand b;
out_nor <= a nor b;
out_xnor <= a xnor b;
out_anotb <= (a and (not b));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:31:46
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, out_and, out_or, out_xor, out_nand, out_nor, out_xnor, out_anotb);
input a;
input b;
output out_and;
output out_or;
output out_xor;
output out_nand;
output out_nor;
output out_xnor;
output out_anotb;
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = a ~^ b;
assign out_anotb = (a & ((~b)));
endmodule
3.1.7 7420 chip
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
p1a, p1b, p1c, p1d : in std_logic;
p1y : out std_logic;
p2a, p2b, p2c, p2d : in std_logic;
p2y : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
p1y <= not(p1a and p1b and p1c and p1d);
p2y <= not(p2d and p2c and p2b and p2a);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:36:24
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(p1a, p1b, p1c, p1d, p1y, p2a, p2b, p2c, p2d, p2y);
input p1a;
input p1b;
input p1c;
input p1d;
output p1y;
input p2a;
input p2b;
input p2c;
input p2d;
output p2y;
assign p1y = (~(p1a & p1b & p1c & p1d));
assign p2y = (~(p2d & p2c & p2b & p2a));
endmodule
3.1.8 Truthtable1
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port (
x3 : in std_logic;
x2 : in std_logic;
x1 : in std_logic;
f : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
f <= (x3=0 and x2=1) or (x3=1 and x1=1);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:43:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x3, x2, x1, f);
input x3;
input x2;
input x1;
output f;
assign f = (x3 == 0 & x2 == 1) | (x3 == 1 & x1 == 1);
endmodule
3.1.9 Two-bit equality
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port (
A: in std_logic_vector (1 downto 0);
B: in std_logic_vector (1 downto 0);
z: out std_logic
);
end top_module;
architecture rtl of top_module is
begin
z <= A=B;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:47:47
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(A, B, z);
input [1:0] A;
input [1:0] B;
output z;
assign z = A == B;
endmodule
3.1.10 Simple circuit A
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
x : in std_logic;
y : in std_logic;
z : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
z <= (x xor y) and x;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:52:10
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, y, z);
input x;
input y;
output z;
assign z = (x ^ y) & x;
endmodule
3.1.11 Simple circuit B
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
x : in std_logic;
y : in std_logic;
z : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
z <= x xnor y;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 11:53:52
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, y, z);
input x;
input y;
output z;
assign z = x ~^ y;
endmodule
3.1.12 Combine circuits A and B
function里不可用signal:
ChatGPT-3.5有言：
在 VHDL 中，函数的参数不能使用
signal关键字来声明，因为函数是一种纯粹的计算机制，只能进行纯粹的计算操作，不能包含状态元素（如信号）。因此，函数参数应该使用in,out,inout或者access等关键字来声明，而不能使用signal关键字。另外，信号
z也不能在函数中声明，因为函数内部不能包含状态元素。
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
x : in std_logic;
y : in std_logic;
z : out std_logic
);
end top_module;
architecture rtl of top_module is
signal IA1_z, IB1_z, IA2_z, IB2_z : std_logic;
function A (signal x, y: in std_logic) return std_logic is
variable z : std_logic;
begin
z := (x xor y) and x;
return z;
end function;
function B (signal x, y: in std_logic) return std_logic is
variable z : std_logic;
begin
z := x xnor y;
return z;
end function;
begin
IA1_z <= A(x => x, y => y);
IB1_z <= B(x => x, y => y);
IA2_z <= A(x => x, y => y);
IB2_z <= B(x => x, y => y);
z<= (IA1_z or IB1_z) xor (IA2_z and IB2_z);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 14:43:11
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, y, z);
input x;
input y;
output z;
wire IA1_z;
wire IB1_z;
wire IA2_z;
wire IB2_z;
function A;
input x;
input y;
reg z;
begin
z = (x ^ y) & x;
A = z;
end
endfunction
function B;
input x;
input y;
reg z;
begin
z = x ~^ y;
B = z;
end
endfunction
assign IA1_z = A(x, y);
assign IB1_z = B(x, y);
assign IA2_z = A(x, y);
assign IB2_z = B(x, y);
assign z = (IA1_z | IB1_z) ^ (IA2_z & IB2_z);
endmodule
3.1.13 Ring or vibrate?
我用的X-HDL 4.2.1，似乎还不支持process(all)，然后我直接使用process(ring, vibrate_mode)，
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
ring : in std_logic;
vibrate_mode : in std_logic;
ringer : out std_logic;
motor : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
--process(all)begin
process(ring, vibrate_mode)begin
if(ring = '1')then
if(vibrate_mode = '1')then
motor <= '1';
else
motor <= '0';
end if;
else
motor <= '0';
end if;
end process;
process(ring, vibrate_mode)begin
if(ring = '1')then
if(vibrate_mode = '1')then
ringer <= '0';
else
ringer<= '1';
end if;
else
ringer <= '0';
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 6 2024 15:01:03
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(ring, vibrate_mode, ringer, motor);
input ring;
input vibrate_mode;
output ringer;
reg ringer;
output motor;
reg motor;
always @(ring or vibrate_mode)
if (ring == 1'b1)
begin
if (vibrate_mode == 1'b1)
begin
motor <= 1'b1;
ringer <= 1'b0;
end
else
begin
motor <= 1'b0;
ringer <= 1'b1;
end
end
else
begin
motor <= 1'b0;
ringer <= 1'b0;
end
endmodule
转换成非阻塞赋值我也是服了，准备更换工具。
本人尝试了以下3个工具
- chiselverify/vhdl2verilog (github.com)：安装环境没有配置成功，没有进行转换。
- edautils.com/DownloadLinks.html：Windows配置失败，Centos配置成功。然而转换结果与X-HDL相同。
折腾一下午+一晚上后：依然使用X-HDL转换，但是转换前将VHDL过一遍Modelsim编译，没有语法错误后，直接测试转换后的.v（不对转换后的.v进行任何修改）
3.1.14 Thermostat
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
too_cold, too_hot, mode, fan_on : in std_logic;
heater, aircon, fan : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
--process(too_cold, mode, too_hot, fan_on)begin
-- if mode = '1' then
-- if too_cold = '1' then
-- heater <= '1';
-- fan <= '1';
-- else
-- heater <= '0';
-- fan <= '1' when fan_on = '1' else '0';
-- end if;
-- aircon <= '0';
-- else
-- if too_hot = '1' then
-- aircon <= '1';
-- fan <= '1';
-- else
-- aircon <= '0';
-- fan <= '1' when fan_on = '1' else '0';
-- end if;
-- heater <= '0';
-- end if;
process(too_cold, mode, too_hot, fan_on)begin
if mode = '1' then
if too_cold = '1' then
heater <= '1';
fan <= '1';
else
heater <= '0';
if fan_on ='1' then
fan <= '1';
else
fan <= '0';
end if;
end if;
aircon <= '0';
else
if too_hot = '1' then
aircon <= '1';
fan <= '1';
else
aircon <= '0';
if fan_on ='1' then
fan <= '1';
else
fan <= '0';
end if;
end if;
heater <= '0';
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 7 2024 11:31:23
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(too_cold, too_hot, mode, fan_on, heater, aircon, fan);
input too_cold;
input too_hot;
input mode;
input fan_on;
output heater;
reg heater;
output aircon;
reg aircon;
output fan;
reg fan;
always @(too_cold or mode or too_hot or fan_on)
if (mode == 1'b1)
begin
if (too_cold == 1'b1)
begin
heater <= 1'b1;
fan <= 1'b1;
end
else
begin
heater <= 1'b0;
if (fan_on == 1'b1)
fan <= 1'b1;
else
fan <= 1'b0;
end
aircon <= 1'b0;
end
else
begin
if (too_hot == 1'b1)
begin
aircon <= 1'b1;
fan <= 1'b1;
end
else
begin
aircon <= 1'b0;
if (fan_on == 1'b1)
fan <= 1'b1;
else
fan <= 1'b0;
end
heater <= 1'b0;
end
endmodule
3.1.15 3-bit population count
https://hdlbits.01xz.net/wiki/Popcount3
注：虽然case的条件都全了，但是还是要写上others！！！
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
in : in std_logic_vector(2 downto 0);
out : out std_logic_vector(1 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(in)is
begin
case (in) is
when "000" => out <= "00";
when "001" | "010" | "100" => out <= "01";
when "011" | "101" | "110" => out <= "10";
when "111" => out <= "11";
when others => out <= "00";-- must has others
end case;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 7 2024 16:01:40
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, out);
input [2:0] in;
output [1:0] out;
reg [1:0] out;
always @(in)
case (in)
3'b000 :
out <= 2'b00;
3'b001, 3'b010, 3'b100 :
out <= 2'b01;
3'b011, 3'b101, 3'b110 :
out <= 2'b10;
3'b111 :
out <= 2'b11;
default :
out <= 2'b00;
endcase
endmodule
3.1.16 Gates and vectors
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
in : in std_logic_vector (3 downto 0);
out_both : out std_logic_vector (2 downto 0);
out_any : out std_logic_vector (3 downto 1);
out_different : out std_logic_vector (3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
out_both(2) <= in(3) and in(2);
out_both(1) <= in(2) and in(1);
out_both(0) <= in(1) and in(0);
out_any(3) <= in(3) or in(2);
out_any(2) <= in(2) or in(1);
out_any(1) <= in(1) or in(0);
out_different(3) <= in(0) xor in(3);
out_different(2) <= in(3) xor in(2);
out_different(1) <= in(2) xor in(1);
out_different(0) <= in(1) xor in(0);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 7 2024 16:13:49
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, out_both, out_any, out_different);
input [3:0] in;
output [2:0] out_both;
output [3:1] out_any;
output [3:0] out_different;
assign out_both[2] = in[3] & in[2];
assign out_both[1] = in[2] & in[1];
assign out_both[0] = in[1] & in[0];
assign out_any[3] = in[3] | in[2];
assign out_any[2] = in[2] | in[1];
assign out_any[1] = in[1] | in[0];
assign out_different[3] = in[0] ^ in[3];
assign out_different[2] = in[3] ^ in[2];
assign out_different[1] = in[2] ^ in[1];
assign out_different[0] = in[1] ^ in[0];
endmodule
3.1.17 Even longer vectors
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
in : in std_logic_vector (99 downto 0);
out_both : out std_logic_vector (98 downto 0);
out_any : out std_logic_vector (99 downto 1);
out_different : out std_logic_vector (99 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
ob:for i in 0 to 98 generate
out_both(i) <= in(i+1) and in(i);
out_any(i+1) <= in(i+1) or in(i);
out_different(i) <= in(i+1) xor in(i);
end generate;
out_different(99) <= in(0) xor in(99);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 7 2024 16:25:00
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, out_both, out_any, out_different);
input [99:0] in;
output [98:0] out_both;
output [99:1] out_any;
output [99:0] out_different;
generate
begin : xhdl0
genvar i;
for (i = 0; i <= 98; i = i + 1)
begin : ob
assign out_both[i] = in[i + 1] & in[i];
assign out_any[i + 1] = in[i + 1] | in[i];
assign out_different[i] = in[i + 1] ^ in[i];
end
end
endgenerate
assign out_different[99] = in[0] ^ in[99];
endmodule
3.2 刷题二： Combinational Logic Multiplexers
3.2.1 2-to-1 multiplexer
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,sel : in std_logic ;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(sel) is
begin
case(sel) is
when '0' => out <= a;
when '1' => out <= b;
when others => out <= a;
end case;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 09:51:30
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, sel, out);
input a;
input b;
input sel;
output out;
reg out;
always @(sel)
case (sel)
1'b0 :
out <= a;
1'b1 :
out <= b;
default :
out <= a;
endcase
endmodule
3.2.2 2-to-1 bus multiplexer
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b : in std_logic_vector (99 downto 0);
sel : in std_logic;
out : out std_logic_vector(99 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(sel)is
begin
case(sel) is
when '0' => out <= a;
when '1' => out <= b;
when others => out <= a;
end case;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 09:57:13
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, sel, out);
input [99:0] a;
input [99:0] b;
input sel;
output [99:0] out;
reg [99:0] out;
always @(sel)
case (sel)
1'b0 :
out <= a;
1'b1 :
out <= b;
default :
out <= a;
endcase
endmodule
3.2.3 9-to-1 multiplexer
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c,d,e,f,g,h,i : in std_logic_vector (15 downto 0);
sel : in std_logic_vector (3 downto 0);
out : out std_logic_vector(15 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(sel,a,b,c,d,e,f,g,h,i)is
begin
case(sel) is
when "0000" => out <= a;
when "0001" => out <= b;
when "0010" => out <= c;
when "0011" => out <= d;
when "0100" => out <= e;
when "0101" => out <= f;
when "0110" => out <= g;
when "0111" => out <= h;
when "1000" => out <= i;
when others => out <= X"FFFF";
end case;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 10:02:20
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, d, e, f, g, h, i, sel, out);
input [15:0] a;
input [15:0] b;
input [15:0] c;
input [15:0] d;
input [15:0] e;
input [15:0] f;
input [15:0] g;
input [15:0] h;
input [15:0] i;
input [3:0] sel;
output [15:0] out;
reg [15:0] out;
always @(sel)
case (sel)
4'b0000 :
out <= a;
4'b0001 :
out <= b;
4'b0010 :
out <= c;
4'b0011 :
out <= d;
4'b0100 :
out <= e;
4'b0101 :
out <= f;
4'b0110 :
out <= g;
4'b0111 :
out <= h;
4'b1000 :
out <= i;
default :
out <= 16'hFFFF;
endcase
endmodule
3.2.4 256-to-1 multiplexer
本题答案来自chatGPT-3.5
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_module is
port (
in : in std_logic_vector(255 downto 0);
sel : in std_logic_vector(7 downto 0);
out : out std_logic
);
end top_module;
architecture behavioral of top_module is
begin
process (sel, in)
begin
case to_integer(unsigned(sel)) is
when 0 =>
out <= in(0);
when others =>
out <= in(to_integer(unsigned(sel)));
end case;
end process;
end behavioral;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 10:13:12
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, sel, out);
input [255:0] in;
input [7:0] sel;
output out;
reg out;
always @(sel or in)
case (sel)
0 :
out <= in[0];
default :
out <= in[sel];
endcase
endmodul
3.2.5 256-to-1 4-bit multiplexer
参考：256-1多路选择器的Verilog实现思路(HDLbits_Mux256to1v)_verilog256选一选择器-CSDN博客
- 256-1多路选择器的Verilog实现思路(HDLbits_Mux256to1v)_verilog256选一选择器-CSDN博客链接中说Verilog不能直接片选4-bit，但是可以一个bit一个bit地选，最后拼接起来。VHDL也是这样
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_module is
port (
in : in std_logic_vector(1023 downto 0);
sel : in std_logic_vector(7 downto 0);
out : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
constant INPUT_WIDTH : integer := 4;
begin
-- 必须一个bit,一个bit地写
out(3) <= in((sel * INPUT_WIDTH + INPUT_WIDTH - 1));
out(2) <= in((sel * INPUT_WIDTH + INPUT_WIDTH - 2));
out(1) <= in((sel * INPUT_WIDTH + INPUT_WIDTH - 3));
out(0) <= in((sel * INPUT_WIDTH + INPUT_WIDTH - 4));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 11:05:07
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(in, sel, out);
input [1023:0] in;
input [7:0] sel;
output [3:0] out;
parameter INPUT_WIDTH = 4;
assign out[3] = in[(sel * INPUT_WIDTH + INPUT_WIDTH - 1)];
assign out[2] = in[(sel * INPUT_WIDTH + INPUT_WIDTH - 2)];
assign out[1] = in[(sel * INPUT_WIDTH + INPUT_WIDTH - 3)];
assign out[0] = in[(sel * INPUT_WIDTH + INPUT_WIDTH - 4)];
endmodule
3.3 刷题三：Arithmetic Circuits
VHDL的Library，摘自：三、VHDL语言基础 - 阿傥 - 博客园 (cnblogs.com)
- 1.STD_LOGIC_1164程序包
STD_LOGIC_1164程序包定义了一些数据类型、子类型和函数。数据类型包括：STD_ULOGIC、STD_ULOGIC _VECTOR、STD_LOGIC和STD_LOGIC _VECTOR，用的最多最广的是STD_LOGIC和STD_LOGIC_VECTOR数据类型。调用STD_LOGIC_1164程序包中的项目需要使用以下语句：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
该程序包预先在IEEE库中编译，是IEEE库中最常用的标准程序包，其数据类型能够满足工业标准，非常适合CPLD（或FPGA）器件的多值逻辑设计结构。- 2.STD_LOGIC_ARITH程序包
该程序包是美国Synopsys公司的程序包，预先编译在IEEE库中。主要是在STD_LOGIC_1164程序包的基础上扩展了UNSIGNED（无符号）、SIGNED（符号）和SMALL_INT（短整型）三个数据类型，并定义了相关的算术运算符和转换函数。- 3.STD_LOGIC_SIGNED程序包
该程序包预先编译在IEEE库中，也是Synopsys公司的程序包。主要定义有符号数的运算，重载后可用于INTEGER（整数）、STD_LOGIC（标准逻辑位）和STD_LOGIC _VECTOR（标准逻辑位向量）之间的混合运算，并且定义了STD_LOGIC _VECTOR到INTEGER的转换函数。还定义了STD_LOGIC _VECTOR类型的符号数算数运算子程序。- 4.STD_LOGIC_UNSIGNED程序包
该程序包用来定义无符号数的运算，其他功能与STD_LOGIC_SIGNED相似。
3.3.1 Half adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top_module is
port(
a,b : in std_logic;
cout,sum : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
sum <= a xor b;
cout <= a and b;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 14:52:54
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, cout, sum);
input a;
input b;
output cout;
output sum;
assign sum = a ^ b;
assign cout = a & b;
endmodule
3.3.2 Full adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top_module is
port(
a,b,cin: in std_logic;
cout,sum : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 14:56:04
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, cin, cout, sum);
input a;
input b;
input cin;
output cout;
output sum;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
3.3.3 3-bit binary adder
测试的时候，需要把上小一小节生成的Verilog代码也要拷贝进来，其名修改为：top_module → \rightarrow →full_adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity full_adder is
port(
a,b,cin: in std_logic;
cout,sum : out std_logic
);
end full_adder;
architecture rtl of full_adder is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end rtl;
entity top_module is
port(
a,b : in std_logic_vector (2 downto 0);
cin : in std_logic;
cout, sum : out std_logic_vector (2 downto 0)
);
end top_module;
architecture rtl of top_module is
component full_adder is
port(
a,b,cin: in std_logic;
cout,sum : out std_logic
);
end component;
begin
FA1 : full_adder port map(a => a(0) , b => b(0), cin => cin,
cout => cout(0), sum => sum(0));
FA2 : full_adder port map(a => a(1) , b => b(1), cin => cout(0),
cout => cout(1), sum => sum(1));
FA3 : full_adder port map(a => a(2) , b => b(2), cin => cout(1),
cout => cout(2), sum => sum(2));
end rtl;
module full_adder(a, b, cin, cout, sum);
input a;
input b;
input cin;
output cout;
output sum;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 15:11:06
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, cin, cout, sum);
input [2:0] a;
input [2:0] b;
input cin;
output [2:0] cout;
output [2:0] sum;
full_adder FA1(.a(a[0]), .b(b[0]), .cin(cin), .cout(cout[0]), .sum(sum[0]));
full_adder FA2(.a(a[1]), .b(b[1]), .cin(cout[0]), .cout(cout[1]), .sum(sum[1]));
full_adder FA3(.a(a[2]), .b(b[2]), .cin(cout[1]), .cout(cout[2]), .sum(sum[2]));
endmodule
3.3.4 Adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity full_adder is
port(
a,b,cin: in std_logic;
cout,sum : out std_logic
);
end full_adder;
architecture rtl of full_adder is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end rtl;
entity top_module is
port(
x : in std_logic_vector (3 downto 0);
y : in std_logic_vector (3 downto 0);
sum : out std_logic_vector (4 downto 0)
);
end top_module;
architecture rtl of top_module is
component full_adder is
port(
a,b,cin: in std_logic;
cout,sum : out std_logic
);
end component;
signal cout : std_logic_vector(2 downto 0);
begin
FA1 : full_adder port map( a => x(0) , b => y(0), cin => ('0'),
cout => cout(0), sum => sum(0));
FA2 : full_adder port map( a => x(1) , b => y(1), cin => (cout(0)),
cout => cout(1), sum => sum(1));
FA3 : full_adder port map( a => x(2) , b => y(2), cin => (cout(1)),
cout => cout(2), sum => sum(2));
FA4 : full_adder port map( a => x(3) , b => y(3), cin => (cout(2)),
cout => sum(4), sum => sum(3));
end rtl;
module full_adder(a, b, cin, cout, sum);
input a;
input b;
input cin;
output cout;
output sum;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 15:32:29
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, y, sum);
input [3:0] x;
input [3:0] y;
output [4:0] sum;
wire [2:0] cout;
full_adder FA1(.a(x[0]), .b(y[0]), .cin((1'b0)), .cout(cout[0]), .sum(sum[0]));
full_adder FA2(.a(x[1]), .b(y[1]), .cin((cout[0])), .cout(cout[1]), .sum(sum[1]));
full_adder FA3(.a(x[2]), .b(y[2]), .cin((cout[1])), .cout(cout[2]), .sum(sum[2]));
full_adder FA4(.a(x[3]), .b(y[3]), .cin((cout[2])), .cout(sum[4]), .sum(sum[3]));
endmodule
3.3.5 Signed addition overflow
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
entity top_module is
port(
a,b : in std_logic_vector (7 downto 0);
s : out std_logic_vector(7 downto 0);
overflow: out std_logic
);
end top_module;
architecture rtl of top_module is
signal sum : std_logic_vector (8 downto 0);
begin
sum <= (unsigned(a)) + ((unsigned(b)));
s <= sum(7 downto 0);
overflow <= (a(7) and b(7) and (not sum(7)) )
or ((not a(7)) and (not b(7) and sum(7)));
--assign alu_add_ov = ( add_din1[31] & add_din2[31] & (~result_add[31]) )
-- |( (~add_din1[31]) & (~add_din2[31] & result_add[31]) );
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 16:04:43
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, s, overflow);
input [7:0] a;
input [7:0] b;
output [7:0] s;
output overflow;
wire [8:0] sum;
assign sum = (a) + ((b));
assign s = sum[7:0];
assign overflow = (a[7] & b[7] & ((~sum[7]))) | (((~a[7])) & ((~b[7]) & sum[7]));
endmodule
3.3.6 100-bit binary adder
注意：这里的result <= ('0' & A) + ('0' & B) + cin;!!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity top_module is
port(
a,b : in std_logic_vector (99 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector (99 downto 0)
);
end top_module;
architecture rtl of top_module is
signal result : std_logic_vector (100 downto 0);
begin
result <= ('0' & A) + ('0' & B) + cin;
cout <= result(100);
sum <= result(99 downto 0);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 18:16:12
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, cin, cout, sum);
input [99:0] a;
input [99:0] b;
input cin;
output cout;
output [99:0] sum;
wire [100:0] result;
assign result = ({1'b0, a}) + ({1'b0, b}) + cin;
assign cout = result[100];
assign sum = result[99:0];
endmodule
3.3.7 4-digit BCD adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity top_module is
port(
a,b : in std_logic_vector (15 downto 0);
cin : in std_logic;
cout: out std_logic;
sum : out std_logic_vector (15 downto 0)
);
end top_module;
architecture rtl of top_module is
component bcd_fadd is
port(
a,b : in std_logic_vector (3 downto 0);
cin : in std_logic;
cout: out std_logic;
sum : out std_logic_vector (3 downto 0)
);
end component;
signal carry_out : std_logic_vector (2 downto 0);
begin
BF1: bcd_fadd port map( a => a(3 downto 0), b => b(3 downto 0), cin => cin , cout => carry_out(0), sum => sum(3 downto 0));
BF2: bcd_fadd port map( a => a(7 downto 4), b => b(7 downto 4), cin => carry_out(0), cout => carry_out(1), sum => sum(7 downto 4));
BF3: bcd_fadd port map( a => a(11 downto 8), b => b(11 downto 8), cin => carry_out(1), cout => carry_out(2), sum => sum(11 downto 8));
BF4: bcd_fadd port map( a => a(15 downto 12),b => b(15 downto 12),cin => carry_out(2), cout => cout , sum => sum(15 downto 12));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 18:33:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, cin, cout, sum);
input [15:0] a;
input [15:0] b;
input cin;
output cout;
output [15:0] sum;
wire [2:0] carry_out;
bcd_fadd BF1(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(carry_out[0]), .sum(sum[3:0]));
bcd_fadd BF2(.a(a[7:4]), .b(b[7:4]), .cin(carry_out[0]), .cout(carry_out[1]), .sum(sum[7:4]));
bcd_fadd BF3(.a(a[11:8]), .b(b[11:8]), .cin(carry_out[1]), .cout(carry_out[2]), .sum(sum[11:8]));
bcd_fadd BF4(.a(a[15:12]), .b(b[15:12]), .cin(carry_out[2]), .cout(cout), .sum(sum[15:12]));
endmodule
3.3 刷题三：Karnaugh Map to Circuit
3.3.1 3-variable
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= a or b or c;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 18:40:25
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, out);
input a;
input b;
input c;
output out;
assign out = a | b | c;
endmodule
3.3.2 4-variable
直接用之前写的脚本：真值表 && 逻辑表达式(二)_python真值表转换多项式表带试-CSDN博客
根据化简结果得到如下代码：
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c,d : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out <= ((not a) and b and c)
or (a and (not b) and d )
or (a and c and d )
or ((not b) and (not c))
or ((not a) and (not d));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 18:50:08
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, d, out);
input a;
input b;
input c;
input d;
output out;
assign out = (((~a)) & b & c) | (a & ((~b)) & d) | (a & c & d) | (((~b)) & ((~c))) | (((~a)) & ((~d)));
endmodule
3.3.3 4-variable
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c,d : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
-- s[1]&(~s[2])&(~s[3]) | (~s[1])&s[2] | s[0]&(~s[3]) | s[0]&s[3]
out <= (b and (not c) and (not d) ) or ((not b) and c ) or( a and (not d) ) or (a and d);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 18:59:30
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, d, out);
input a;
input b;
input c;
input d;
output out;
assign out = (b & ((~c)) & ((~d))) | (((~b)) & c) | (a & ((~d))) | (a & d);
endmodule
3.3.4 4-variable
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c,d : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
--(~s[0])&(~s[1])&(~s[2])&s[3] | (~s[0])&(~s[1])&s[2]&(~s[3]) | (~s[0])&s[1]&(~s[2])&(~s[3]) | (~s[0])&s[1]&s[2]&s[3] | s[0]&(~s[1])&(~s[2])&(~s[3]) | s[0]&(~s[1])&s[2]&s[3] | s[0]&s[1]&(~s[2])&s[3] | s[0]&s[1]&s[2]&(~s[3])
out <= ((not a) and (not b) and (not c) and d ) or ( (not a) and (not b) and c and (not d) ) or ( (not a) and b and (not c) and (not d) ) or ( (not a) and b and c and d ) or ( a and (not b) and (not c) and (not d) ) or ( a and (not b) and c and d ) or ( a and b and (not c) and d ) or ( a and b and c and (not d));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 20:16:38
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, d, out);
input a;
input b;
input c;
input d;
output out;
assign out = (((~a)) & ((~b)) & ((~c)) & d) | (((~a)) & ((~b)) & c & ((~d))) | (((~a)) & b & ((~c)) & ((~d))) | (((~a)) & b & c & d) | (a & ((~b)) & ((~c)) & ((~d))) | (a & ((~b)) & c & d) | (a & b & ((~c)) & d) | (a & b & c & ((~d)));
endmodule
3.3.5 Minimum SOP and POS
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
a,b,c,d : in std_logic;
out_sop, out_pos : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
out_sop <= (c and d) or (not a and not b and c);
out_pos <= c and (not a or d) and (not b or d);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 20:41:10
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(a, b, c, d, out_sop, out_pos);
input a;
input b;
input c;
input d;
output out_sop;
output out_pos;
assign out_sop = (c & d) | ((~a) & (~b) & c);
assign out_pos = c & ((~a) | d) & ((~b) | d);
endmodule
3.3.6 Karnaugh map
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
x: in std_logic_vector (4 downto 1);
f: out std_logic
);
end top_module;
architecture rtl of top_module is
begin
f <= (x(1) and (not x(3)) and (not x(4)) )or( x(1) and x(2) and (not x(3)) )or( (not x(2)) and (not x(4)) )or( (not x(1)) and x(3) )or( x(3) and x(4) )or( x(2) and x(4));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 20:46:29
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, f);
input [4:1] x;
output f;
assign f = (x[1] & ((~x[3])) & ((~x[4]))) | (x[1] & x[2] & ((~x[3]))) | (((~x[2])) & ((~x[4]))) | (((~x[1])) & x[3]) | (x[3] & x[4]) | (x[2] & x[4]);
endmodule
3.3.7 Karnaugh map
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
x: in std_logic_vector (4 downto 1);
f: out std_logic
);
end top_module;
architecture rtl of top_module is
begin
f <= (x(2) and x(3) and x(4) )or( (not x(2)) and (not x(4)) )or( (not x(1)) and x(3));
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 20:50:17
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(x, f);
input [4:1] x;
output f;
assign f = (x[2] & x[3] & x[4]) | (((~x[2])) & ((~x[4]))) | (((~x[1])) & x[3]);
endmodule
3.3.8 K-map implemented with a multiplexer
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
c,d: in std_logic;
mux_in: out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
mux_in(0) <= c or d;
mux_in(1) <= '0';
mux_in(2) <= not d;
mux_in(3) <= c and d;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 10 2024 21:03:29
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(c, d, mux_in);
input c;
input d;
output [3:0] mux_in;
assign mux_in[0] = c | d;
assign mux_in[1] = 1'b0;
assign mux_in[2] = (~d);
assign mux_in[3] = c & d;
endmodule
3.4 刷题四：Latches and Flip-Flops
摘自：vhdl rising_edge(clk) (clk’event and clk=‘1’)的区别-CSDN博客
rising_edge 是非常严格的上升沿，必须从0到1 ， (clk’event and clk=‘1’)可以从X到1
查看rising_edge原型
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE) = '0')); END;the statement (clk’event and clk=‘1’) results TRUE when the present value is ‘1’ and there is an edge transition in the clk.It doesnt see whether the previous value is ‘0’ or not.
3.4.1 D flip-flop
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk, d)begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;
生成的verilog中是always @(posedge clk or d)，应该把d去掉的，本人目前没啥办法，只能手动去掉了。
（注：下面就直接删掉了，不再注释！！！）
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 11:18:12
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, d, q);
input clk;
input d;
output q;
reg q;
//always @(posedge clk or d)
always @(posedge clk)
q <= d;
endmodule
3.4.2 D flip-flops
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 11:21:31
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, d, q);
input clk;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(posedge clk)
q <= d;
endmodule
3.4.3 DFF with reset
注意复位的表达： q <= (others => '0');
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset:in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk) then
if reset = '1'then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 11:28:58
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, d, q);
input clk;
input reset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= {8{1'b0}};
else
q <= d;
end
endmodule
记得还要将生成的Verilog代码中的敏感列表中的reset给删掉。
3.4.4 DFF with reset value
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset:in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk, reset)begin
if falling_edge(clk) then
if reset = '1'then
q <= X"34";
else
q <= d;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 11:34:08
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, d, q);
input clk;
input reset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(negedge clk)
begin
if (reset == 1'b1)
q <= 8'h34;
else
q <= d;
end
endmodule
3.4.5 DFF with asynchronous resest
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
areset:in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk, areset)begin
if areset = '1'then
q <= (others => '0');
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 11:57:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, areset, d, q);
input clk;
input areset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(posedge clk or posedge areset)
if (areset == 1'b1)
q <= {8{1'b0}};
else
q <= d;
endmodule
3.4.6 DFF with byte enable
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk: in std_logic;
resetn : in std_logic;
byteena : in std_logic_vector (1 downto 0);
d : in std_logic_vector (15 downto 0);
q : out std_logic_vector(15 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
if resetn = '0' then
q <= (others => '0');
else
if byteena(0) = '1' then
q(7 downto 0) <= d( 7 downto 0);
end if;
if byteena(1) = '1' then
q(15 downto 8) <= d(15 downto 8);
end if;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 15:16:43
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, resetn, byteena, d, q);
input clk;
input resetn;
input [1:0] byteena;
input [15:0] d;
output [15:0] q;
reg [15:0] q;
always @(posedge clk)
begin
if (resetn == 1'b0)
q <= {16{1'b0}};
else
begin
if (byteena[0] == 1'b1)
q[7:0] <= d[7:0];
if (byteena[1] == 1'b1)
q[15:8] <= d[15:8];
end
end
endmodule
3.4.7 D Latch
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(d, ena)begin
if(ena)then
q <= d;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 15:23:14
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(d, ena, q);
input d;
input ena;
output q;
reg q;
always @(d or ena)
if (ena)
q <= d;
endmodule
3.4.8 DFF
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
d : in std_logic;
ar : in std_logic;
q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk, ar)begin
if ar = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 15:46:49
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, d, ar, q);
input clk;
input d;
input ar;
output q;
reg q;
always @(posedge clk or posedge ar)
if (ar == 1'b1)
q <= 1'b0;
else
q <= d;
endmodule
3.4.9 DFF
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
d : in std_logic;
r : in std_logic;
q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk) then
if r = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:04:46
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, d, r, q);
input clk;
input d;
input r;
output q;
reg q;
always @(posedge clk)
begin
if (r == 1'b1)
q <= 1'b0;
else
q <= d;
end
endmodule
3.4.10 DFF+gate
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
in : in std_logic;
out : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
out <= in xor out;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:25:42
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, in, out);
input clk;
input in;
output out;
reg out;
always @(posedge clk)
out <= in ^ out;
endmodule
3.4.11 Mux and DFF
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk,L,r_in,q_in: in std_logic;
Q : out std_logic
);
end top_module;
architecture rtl of top_module is
--signal Q0,Q1,Q2 : std_logic;
begin
process(clk)begin
if rising_edge(clk)then
if L = '1' then
Q <= r_in;
else
Q <= q_in;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:32:26
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, L, r_in, q_in, Q);
input clk;
input L;
input r_in;
input q_in;
output Q;
reg Q;
always @(posedge clk)
begin
if (L == 1'b1)
Q <= r_in;
else
Q <= q_in;
end
endmodule
3.4.12 Mux and DFF
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, w, R, E, L : in std_logic;
Q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk) then
if L = '1' then
Q <= R;
else
if E = '1' then
Q <= w;
else
null;
end if;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:37:31
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, w, R, E, L, Q);
input clk;
input w;
input R;
input E;
input L;
output Q;
reg Q;
always @(posedge clk)
begin
if (L == 1'b1)
Q <= R;
else
if (E == 1'b1)
Q <= w;
else
;
end
endmodule
3.4.13 DFFs and gates
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, x : in std_logic;
z : out std_logic
);
end top_module;
architecture rtl of top_module is
signal q1, q2, q3 : std_logic;
begin
process(clk) is begin
if rising_edge(clk)then
q1 <= x xor q1;
q2 <= x and (not q2);
q3 <= x or (not q3);
end if;
end process;
z <= not(q1 or q2 or q3);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:41:40
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, x, z);
input clk;
input x;
output z;
reg q1;
reg q2;
reg q3;
always @(posedge clk)
begin
q1 <= x ^ q1;
q2 <= x & ((~q2));
q3 <= x | ((~q3));
end
assign z = (~(q1 | q2 | q3));
endmodule
3.4.14 Create cirtuit from truth table
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, j, k: in std_logic;
Q : out std_logic
);
end top_module;
architecture rtl of top_module is
begin
process(clk) is begin
if rising_edge(clk)then
case (j&k) is
when "00" => Q <= Q;
when "01" => Q <= '0';
when "10" => Q <= '1';
when "11" => Q <= not(Q);
end case;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 16:45:05
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, j, k, Q);
input clk;
input j;
input k;
output Q;
reg Q;
always @(posedge clk)
case ({j, k})
2'b00 :
Q <= Q;
2'b01 :
Q <= 1'b0;
2'b10 :
Q <= 1'b1;
2'b11 :
Q <= (~(Q));
endcase
endmodule
3.4.15 Detect an edge
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
in : in std_logic_vector(7 downto 0);
pedge: out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
signal in_ff1 : std_logic_vector (7 downto 0);
begin
process(clk)begin
if rising_edge(clk)then
in_ff1 <= in;
end if;
pedge <= (not in_ff1) and in;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 17:12:42
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, in, pedge);
input clk;
input [7:0] in;
output [7:0] pedge;
reg [7:0] pedge;
reg [7:0] in_ff1;
always @(posedge clk)
begin
in_ff1 <= in;
pedge <= ((~in_ff1)) & in;
end
endmodule
3.4.16 Detect both edges
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
in : in std_logic_vector(7 downto 0);
anyedge: out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
signal in_ff1 : std_logic_vector (7 downto 0);
begin
process(clk)begin
if rising_edge(clk)then
in_ff1 <= in;
end if;
anyedge <= in_ff1 xor in;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 18:15:08
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, in, anyedge);
input clk;
input [7:0] in;
output [7:0] anyedge;
reg [7:0] anyedge;
reg [7:0] in_ff1;
always @(posedge clk)
begin
in_ff1 <= in;
anyedge <= in_ff1 ^ in;
end
endmodule
3.4.17 Edge capture register
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset: in std_logic;
in : in std_logic_vector(31 downto 0);
out : out std_logic_vector(31 downto 0)
);
end top_module;
architecture rtl of top_module is
signal in_ff1 : std_logic_vector(31 downto 0);
begin
process(clk)begin
if rising_edge(clk) then
in_ff1 <= in;
end if;
end process;
process(clk)begin
if rising_edge(clk) then
if reset = '1' then
out <= (others => '0');
else
out <= (in_ff1 and not(in)) or out;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 20:01:58
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, in, out);
input clk;
input reset;
input [31:0] in;
output [31:0] out;
reg [31:0] out;
reg [31:0] in_ff1;
always @(posedge clk)
in_ff1 <= in;
always @(posedge clk)
begin
if (reset == 1'b1)
out <= {32{1'b0}};
else
out <= (in_ff1 & (~(in))) | out;
end
endmodule
3.4.18 Dual-edge triggered flip-flop
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end top_module;
architecture rtl of top_module is
signal pq : std_logic;
signal nq : std_logic;
begin
process(clk)begin
if clk'event and clk='1' then
pq <= d;
end if;
end process;
process(clk)begin
if clk'event and clk='0' then
nq <= d;
end if;
end process;
q <= (clk and pq) or (not(clk) and nq);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 11 2024 20:14:23
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, d, q);
input clk;
input d;
output q;
reg pq;
reg nq;
always @(posedge clk)
pq <= d;
always @(negedge clk)
nq <= d;
assign q = (clk & pq) | ((~(clk)) & nq);
endmodule
3.5 刷题五：Counters
3.5.1 Four-bit binary counter
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
q <= (others => '0');
else
q <= q + '1';
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 09:52:22
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, q);
input clk;
input reset;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= {4{1'b0}};
else
q <= q + 1'b1;
end
endmodule
3.5.2 Decade counter
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
q <= (others => '0');
elsif q = X"9" then
q <= (others => '0');
else
q <= q + '1';
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 09:55:10
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, q);
input clk;
input reset;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= {4{1'b0}};
else if (q == 4'h9)
q <= {4{1'b0}};
else
q <= q + 1'b1;
end
endmodule
3.5.3 Decade counter again
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
q <= X"1";
elsif q = X"A" then
q <= X"1";
else
q <= q + '1';
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 10:02:57
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, q);
input clk;
input reset;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= 4'h1;
else if (q == 4'hA)
q <= 4'h1;
else
q <= q + 1'b1;
end
endmodule
3.5.4 Slow decade counter
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk : in std_logic;
reset : in std_logic;
slowena:in std_logic;
q : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
q <= (others => '0');
elsif slowena = '1'then
if q = 9 then
q <= (others => '0');
else
q <= q + '1';
end if;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 10:09:50
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, slowena, q);
input clk;
input reset;
input slowena;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= {4{1'b0}};
else if (slowena == 1'b1)
begin
if (q == 9)
q <= {4{1'b0}};
else
q <= q + 1'b1;
end
end
endmodule
3.5.5 Counter 1-12
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, enable, reset : in std_logic;
Q : out std_logic_vector(3 downto 0);
c_enable : out std_logic;
c_load : out std_logic;
c_d : out std_logic_vector(3 downto 0)
);
end top_module;
architecture rtl of top_module is
component count4 is
port (
clk, enable, load : in std_logic;
d : in std_logic_vector (3 downto 0);
Q : out std_logic_vector(3 downto 0)
);
end component;
begin
process(reset, enable, Q)begin
if reset = '1' then
c_load <= '1';
c_d <= X"1";
else
if enable = '1' and Q = 12 then
c_load <= '1';
c_d <= '1';
else
c_load <= '0';
c_d <= '0';
end if;
end if;
end process;
the_counter : count4 port map(clk => clk, enable => enable, load => c_load,d => c_d, Q => Q);
c_enable <= enable;
end rtl;
X-HDL生成的Verilog有问题，q应该是Q
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 10:38:28
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, enable, reset, Q, c_enable, c_load, c_d);
input clk;
input enable;
input reset;
output [3:0] Q;
output c_enable;
output c_load;
reg c_load;
output [3:0] c_d;
reg [3:0] c_d;
always @(reset or enable or Q)
if (reset == 1'b1)
begin
c_load <= 1'b1;
c_d <= 4'h1;
end
else
if (enable == 1'b1 & Q == 12)
begin
c_load <= 1'b1;
c_d <= 1'b1;
end
else
begin
c_load <= 1'b0;
c_d <= 1'b0;
end
count4 the_counter(.clk(clk), .enable(enable), .load(c_load), .d(c_d), .q(Q));
assign c_enable = enable;
endmodule
3.5.6 Counter 1000
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk,reset : in std_logic;
OneHertz : out std_logic;
c_enable : out std_logic_vector(2 downto 0)
);
end top_module;
architecture rtl of top_module is
component bcdcount is
port (
clk, enable, reset: in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end component;
signal Q0, Q1, Q2 : std_logic_vector(3 downto 0);
begin
process(reset, c_enable, Q0, Q1)begin
if reset = '1' then
c_enable <= (others => '0');
else
c_enable(0) <= '1';
c_enable(1) <= Q0 = X"9";
c_enable(2) <= Q1 = X"9" and Q0 = X"9";
end if;
end process;
counter0 : bcdcount port map(clk => clk, reset => reset,enable => c_enable(0), Q => Q0);
counter1 : bcdcount port map(clk => clk, reset => reset,enable => c_enable(1), Q => Q1);
counter2 : bcdcount port map(clk => clk, reset => reset,enable => c_enable(2), Q => Q2);
OneHertz <= (Q2 = X"9" and Q1 = X"9" and Q0 = X"9");
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 11:02:00
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, OneHertz, c_enable);
input clk;
input reset;
output OneHertz;
output [2:0] c_enable;
reg [2:0] c_enable;
wire [3:0] Q0;
wire [3:0] Q1;
wire [3:0] Q2;
always @(reset or c_enable or Q0 or Q1)
if (reset == 1'b1)
c_enable <= {3{1'b0}};
else
begin
c_enable[0] <= 1'b1;
c_enable[1] <= Q0 == 4'h9;
c_enable[2] <= Q1 == 4'h9 & Q0 == 4'h9;
end
bcdcount counter0(.clk(clk), .reset(reset), .enable(c_enable[0]), .q(Q0));
bcdcount counter1(.clk(clk), .reset(reset), .enable(c_enable[1]), .q(Q1));
bcdcount counter2(.clk(clk), .reset(reset), .enable(c_enable[2]), .q(Q2));
assign OneHertz = (Q2 == 4'h9 & Q1 == 4'h9 & Q0 == 4'h9);
endmodule
X-HDL生成的Verilog有问题，q应该是Q
3.5.7 4-digit decimal counter
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, reset : in std_logic;
ena : out std_logic_vector (3 downto 1);
q : out std_logic_vector (15 downto 0)
);
end top_module;
architecture rtl of top_module is
signal overflow : std_logic;
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
q <= (others => '0');
elsif overflow = '1' then
q (15 downto 0) <= (others => '0');
elsif(ena(3) = '1' )then
q(11 downto 0) <= (others => '0');
q(15 downto 12) <= q (15 downto 12) + '1';
elsif(ena(2) = '1' )then
q(7 downto 0) <= X"0";
q(11 downto 8) <= q(11 downto 8) + '1';
elsif(ena(1) = '1' )then
q(3 downto 0) <= X"0";
q(7 downto 4) <= q(7 downto 4) + '1';
else
q(3 downto 0) <= q(3 downto 0) + '1';
end if;
end if;
end process;
ena(1) <= q(3 downto 0) = X"9";
ena(2) <= (q(7 downto 4) = X"9") and ena(1);
ena(3) <= (q(11 downto 8) = X"9") and ena(2);
overflow <= (q(15 downto 12) = X"9") and ena(3);
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 11:22:33
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, ena, q);
input clk;
input reset;
output [3:1] ena;
output [15:0] q;
reg [15:0] q;
wire overflow;
always @(posedge clk)
begin
if (reset == 1'b1)
q <= {16{1'b0}};
else if (overflow)
q[15:0] <= {16{1'b0}};
else if (ena[3])
begin
q[11:0] <= {16{1'b0}};
q[15:12] <= q[15:12] + 1'b1;
end
else if (ena[2])
begin
q[7:0] <= 4'h0;
q[11:8] <= q[11:8] + 1'b1;
end
else if (ena[1])
begin
q[3:0] <= 4'h0;
q[7:4] <= q[7:4] + 1'b1;
end
else
q[3:0] <= q[3:0] + 1'b1;
end
assign ena[1] = q[3:0] == 4'h9;
assign ena[2] = (q[7:4] == 4'h9) & ena[1];
assign ena[3] = (q[11:8] == 4'h9) & ena[2];
assign overflow = (q[15:12] == 4'h9) & ena[3];
endmodule
3.5.8 12-hour clock
library ieee;
use ieee.std_logic_1164.all;
entity top_module is
port(
clk, reset, ena : in std_logic;
pm : out std_logic;
hh, mm, ss : out std_logic_vector (7 downto 0)
);
end top_module;
architecture rtl of top_module is
signal h_plus, m_plus: std_logic;
begin
process(clk)begin
if rising_edge(clk)then
if reset = '1' then
hh <= X"12";
mm <= X"00";
ss <= X"00";
elsif ena = '1' then
if h_plus ='1' then
mm <= X"00";
ss <= X"00";
if hh = X"12" then
hh <= X"01";
else
if (hh(3 downto 0) = X"9")then
hh(3 downto 0) <= X"0";
hh(7 downto 4) <= hh(7 downto 4) + '1';
else
hh(3 downto 0) <= hh(3 downto 0) + '1';
end if;
end if;
elsif m_plus then
if(mm(3 downto 0) = X"9")then
mm(3 downto 0) <= X"0";
mm(7 downto 4) <= mm(7 downto 4) + '1';
else
mm(3 downto 0) <= mm(3 downto 0) + '1';
end if;
ss <= X"00";
else
if(ss(3 downto 0) = X"9") then
ss(3 downto 0) <= X"0";
ss(7 downto 4) <= ss(7 downto 4) + '1';
else
ss(3 downto 0) <= ss(3 downto 0) + '1';
end if;
end if;
end if;
end if;
end process;
m_plus <= ss = X"59";
h_plus <= (mm = X"59") and m_plus;
process(clk)begin
if rising_edge(clk) then
if reset = '1' then
pm <= '0';
elsif ena = '1' then
if( hh = X"11" and h_plus)then
pm <= not pm;
end if;
end if;
end if;
end process;
end rtl;
//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 13 2024 15:43:01
//
// Input file :
// Component name : top_module
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module top_module(clk, reset, ena, pm, hh, mm, ss);
input clk;
input reset;
input ena;
output pm;
reg pm;
output [7:0] hh;
reg [7:0] hh;
output [7:0] mm;
reg [7:0] mm;
output [7:0] ss;
reg [7:0] ss;
wire h_plus;
wire m_plus;
always @(posedge clk)
begin
if (reset)
begin
hh <= 8'h12;
mm <= 8'h00;
ss <= 8'h00;
end
else if (ena)
begin
if (h_plus)
begin
mm <= 8'h00;
ss <= 8'h00;
if (hh == 8'h12)
hh <= 8'h01;
else
if (hh[3:0] == 4'h9)
begin
hh[3:0] <= 4'h0;
hh[7:4] <= hh[7:4] + 1'b1;
end
else
hh[3:0] <= hh[3:0] + 1'b1;
end
else if (m_plus)
begin
if (mm[3:0] == 4'h9)
begin
mm[3:0] <= 4'h0;
mm[7:4] <= mm[7:4] + 1'b1;
end
else
mm[3:0] <= mm[3:0] + 1'b1;
ss <= 8'h00;
end
else
if (ss[3:0] == 4'h9)
begin
ss[3:0] <= 4'h0;
ss[7:4] <= ss[7:4] + 1'b1;
end
else
ss[3:0] <= ss[3:0] + 1'b1;
end
end
assign m_plus = ss == 8'h59;
assign h_plus = (mm == 8'h59) & m_plus;
always @(posedge clk)
begin
if (reset)
pm <= 1'b0;
else if (ena)
begin
if (hh == 8'h11 & h_plus)
pm <= (~pm);
end
end
endmodule
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