Task And Function （of Verilog HDL)

		Task //任务（task）
		Syntax //语法 Example - Simple Task // 简单的任务举例 Example - Task using Global Variables //使用全局变量的任务 Calling a Task //调用一个任务 Example - CPU Write / Read Task //cpu的读写任务
		Function /函数
		Syntax //语法 Example - Simple Function //简单的函数 Example - Calling a Function //函数的调用

the above original link:http://www.asic-world.com/verilog/task_func.html

		Task //任务
		Tasks are used in all programming languages, generally known as procedures or subroutines. The lines of code are enclosed in task....end task brackets. Data is passed to the task, the processing done, and the result returned. They have to be specifically called, with data ins and outs, rather than just wired in to the general netlist. Included in the main body of code, they can be called many times, reducing code repetition. 所有的编程语言中都有Tasks，通常被称之为过程或者子程序。在task和endtask 关键字之内的代码。数据data传给task，处理完成后，结果返回。 任务需在调用时，需要详细指派数据的输入，输出类型，而不是直接连接到通常的线网类型。在一个代码的主体部分中，他们可能被多次调用，从而减少了代码重复。
		tasks are defined in the module in which they are used. It is possible to define a task in a separate file and use the compile directive 'include to include the task in the file which instantiates the task.   task 可以定义在使用它们的模块之内。也可以在一个独立的文件中定义一个任务task，并且通过编译器的include指令将task包含到要实例化它的文件 tasks can include timing delays, like posedge, negedge, # delay and wait. 在task中可以包含时间延迟，像posedge，negedge，#delay 和wait语句等。 tasks can have any number of inputs and outputs. task可以任意多个inputs和outputs The variables declared within the task are local to that task. The order of declaration within the task defines how the variables passed to the task by the caller are used. task内部声明的变量是该task的局部变量。 task中变量的声明次序决定了变量是如何被调用者传入到task中的。 tasks can take, drive and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of task execution. 当没有局部变量使用时，task可以 take，drive和source 全局变量。当使用局部变量时，输出在task执行结束时被赋值。 tasks can call another task or function. task可以调用另一个task或者function。 tasks can be used for modeling both combinational and sequential logic. task既可以为组合逻辑建模也可以为时序逻辑建模。 A task must be specifically called with a statement, it cannot be used within an expression as a function can. 一个任务只能作为一条具体的调用语句，不能像function函数那样可以用在表达式中。
		Syntax //语法
		A task begins with keyword task and ends with keyword endtask task以 task关键字开始和以endtask关键字结束。 Inputs and outputs are declared after the keyword task. 输入和输出声明在关键字task之后 Local variables are declared after input and output declaration. 局部变量声明在input和output的申明之后
		Example - Simple Task //简单的任务举例
		1 module simple_task(); 2 3 task convert; 4 input [7:0] temp_in; 5 output [7:0] temp_out; 6 begin 7 temp_out = (9/5) *( temp_in + 32) 8 end 9 endtask 10 11 endmodule You could download file simple_task.v here
		Example - Task using Global Variables //使用全局变量的任务
		1 module task_global(); 2 3 reg [7:0] temp_out; 4 reg [7:0] temp_in; 5 6 task convert; 7 begin 8 temp_out = (9/5) *( temp_in + 32); 9 end 10 endtask 11 12 endmodule You could download file task_global.v here
		Calling a Task // 调用一个任务
		Let's assume that the task in example 1 is stored in a file called mytask.v. Advantage of coding a task in a separate file, is that it can be used in multiple modules. 让我们假设例1中那个task保存在一个叫mytask.v的文件中。将task的编码放在一个独立的文件中的好处是它可以在多个模块中使用。
		1 module task_calling (temp_a, temp_b, temp_c, temp_d); 2 input [7:0] temp_a, temp_c; 3 output [7:0] temp_b, temp_d; 4 reg [7:0] temp_b, temp_d; 5 `include "mytask.v" 6 7 always @ (temp_a) 8 begin 9 convert (temp_a, temp_b); 10 end 11 12 always @ (temp_c) 13 begin 14 convert (temp_c, temp_d); 15 end 16 17 endmodule You could download file task_calling.v here
		Example - CPU Write / Read Task //cpu write和read任务
		Below is the waveform used for writing into memory and reading from memory. We make the assumption that there is a need to use this interface from multiple agents. So we write the read/write as tasks. 下面是写入memory和从memory读出的时的波形图。我们假设很多agents使用这个接口。因此，我们将read、write写为一个任务
		1 module bus_wr_rd_task(); 2 3 reg clk,rd,wr,ce; 4 reg [7:0] addr,data_wr,data_rd; 5 reg [7:0] read_data; 6 7 initial begin 8 clk = 0; 9 read_data = 0; 10 rd = 0; 11 wr = 0; 12 ce = 0; 13 addr = 0; 14 data_wr = 0; 15 data_rd = 0; 16 // Call the write and read tasks here 17 #1 cpu_write(8'h11,8'hAA); 18 #1 cpu_read(8'h11,read_data); 19 #1 cpu_write(8'h12,8'hAB); 20 #1 cpu_read(8'h12,read_data); 21 #1 cpu_write(8'h13,8'h0A); 22 #1 cpu_read(8'h13,read_data); 23 #100 $finish; 24 end 25 // Clock Generator 26 always 27 #1 clk = ~clk; 28 // CPU Read Task 29 task cpu_read; 30 input [7:0] address; 31 output [7:0] data; 32 begin 33 $display ("%g CPU Read task with address : %h", $time, address); 34 $display ("%g -> Driving CE, RD and ADDRESS on to bus", $time); 35 @ (posedge clk); 36 addr = address; 37 ce = 1; 38 rd = 1; 39 @ (negedge clk); 40 data = data_rd; 41 @ (posedge clk); 42 addr = 0; 43 ce = 0; 44 rd = 0; 45 $display ("%g CPU Read data : %h", $time, data); 46 $display ("======================"); 47 end 48 endtask 49 // CU Write Task 50 task cpu_write; 51 input [7:0] address; 52 input [7:0] data; 53 begin 54 $display ("%g CPU Write task with address : %h Data : %h", 55 $time, address,data); 56 $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus", 57 $time); 58 @ (posedge clk); 59 addr = address; 60 ce = 1; 61 wr = 1; 62 data_wr = data; 63 @ (posedge clk); 64 addr = 0; 65 ce = 0; 66 wr = 0; 67 $display ("======================"); 68 end 69 endtask 70 71 // Memory model for checking tasks 72 reg [7:0] mem [0:255]; 73 74 always @ (addr or ce or rd or wr or data_wr) 75 if (ce) begin 76 if (wr) begin 77 mem[addr] = data_wr; 78 end 79 if (rd) begin 80 data_rd = mem[addr]; 81 end 82 end 83 84 endmodule You could download file bus_wr_rd_task.v here
		Simulation Output
		1 CPU Write task with address : 11 Data : aa 1 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 4 CPU Read task with address : 11 4 -> Driving CE, RD and ADDRESS on to bus 7 CPU Read data : aa ====================== 8 CPU Write task with address : 12 Data : ab 8 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 12 CPU Read task with address : 12 12 -> Driving CE, RD and ADDRESS on to bus 15 CPU Read data : ab ====================== 16 CPU Write task with address : 13 Data : 0a 16 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 20 CPU Read task with address : 13 20 -> Driving CE, RD and ADDRESS on to bus 23 CPU Read data : 0a ======================
		Function //函数
		A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more than one output, can not contain delays. 一个Verilog HDL的函数和一个task除了一点细微的差别是一样的。如函数function不能驱动多个输出也不能包含延迟。
		functions are defined in the module in which they are used. It is possible to define functions in separate files and use compile directive 'include to include the function in the file which instantiates the function. 函数可以在使用它的模块内定义，同样函数也可以在一个独立的文件中定义，并且可以使用编译器指令include到要将实例化该function的文件中。 functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay. 函数function中不能包含时间延迟，像正沿，负沿，#delay也就是function的执行是没有时延的。 functions can have any number of inputs but only one output. 函数function可以任意多的输入但只有一个输出。 The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used. 函数function中声明的变量是局部变量。 函数的变量的声明的次序是调用者传递给function函数的次序。 functions can take, drive, and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of function execution. 函数function可以take，drive和source全局变量，在函数不适用局部时。 当使用局部变量时，只有基本的输出output在函数执行结束时。 functions can be used for modeling combinational logic. 函数function可以用来为组合逻辑建模 functions can call other functions, but can not call tasks. 函数function可以被其他函数或者task调用，但是不能调用task。
		Syntax //语法
		A function begins with keyword function and ends with keyword endfunction 一个函数function以关键字 function开始，以关键字endfunction结尾。 inputs are declared after the keyword function. 输入input在关键字function之后声明。
		Example - Simple Function //简单任务举例
		1 module simple_function(); 2 3 function myfunction; 4 input a, b, c, d; 5 begin 6 myfunction = ((a+b) + (c-d)); 7 end 8 endfunction 9 10 endmodule You could download file simple_function.v here
		Example - Calling a Function // 函数调用举例
		1 module function_calling(a, b, c, d, e, f); 2 3 input a, b, c, d, e ; 4 output f; 5 wire f; 6 `include "myfunction.v" 7 8 assign f = (myfunction (a,b,c,d)) ? e :0; 9 10 endmodule You could download file function_calling.v here

the above original link：http://www.asic-world.com/verilog/task_func1.html