xilinx平台软件使用
参考博客
基于Zedboard的PetaLinux 2019.1试验
Petalinux 2018.2 for Xilinx
petalinux如何保留u-boot和kernel源码
1 使用Xilinx SDK
1.1 创建工程
ML30S_B2_FPGA_210409.hdf 平台相关文件.
File --> Application project
1.2 加载裸机示例代码
2 petalinux 编译内核
2.1 首先在使用petalinux创建工程并且编译内核
- ① source 环境
source /settings.sh
- ② 创建工程
或者
petalinux-create -t project --template zynqMP -n project_test
-
③ 拷贝平台*.hdf文件到任意路径下
-
④ 执行指令读取平台文件,配置内核
petalinux-config --get-hw-description=./
描述后面填充的是路径 ,平台文件存储的路径
- ⑤ 运行结果如下,出现平台配置界面
- ⑥ 保存退出出现界面
如果出现错误,保存出现失败的情况
2.2 编译内核
petalinux-build -x distclean
petalinux-build 编译内核
2.3 配置内核
petalinux-config -c kernel 类似于make menuconfig
2.4 配置文件系统
petalinux-config -c rootfs
2.5 修改项目配置保留内核源码和uboot源码
因为每新建一个项目,进行编译时都会在线下载内核源码和uboot源码,所以体积会很大。所以编译完毕之后,就删除了内核。
- 修改配置文件,保存内核源码
在project-spec/meta-user/conf/petalinuxbsp.conf里,添加如下内容,可以保留Linux和UBoot源代码。
RM_WORK_EXCLUDE += “linux-xlnx”
RM_WORK_EXCLUDE += “u-boot-xlnx”
对于PetaLinux 2019.1的ZCU106 BSP工程,它在目录build/tmp/work/zcu106_zynqmp-xilinx-linux/linux-xlnx/4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0/linux-zcu106_zynqmp-standard-build/下。
对于PetaLinux 2019.1的ZCU106 BSP工程,UBoot源代码在目录 ./build/tmp/work/zcu106_zynqmp-xilinx-linux/u-boot-xlnx/v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0/git/ 2019.2build/tmp/work/plnx_zynqmp-xilinx-linux/u-boot-xlnx/v2019.01-xilinx-v2019.2+gitAUTOINC+dc61275b1d-r0/gitbuild/tmp/work/plnx_zynqmp-xilinx-linux/linux-xlnx/4.19-xilinx-v2019.2+gitAUTOINC+b983d5fd71-r0/linux-plnx_zynqmp-standard-build
2.6 内核源码生成路径
/home/xxx/petalinux2019.1/project_pac1934/build/tmp/work-shared/plnx-zynqmp/kernel-source
2.7 设备树路径
-
https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview
wiki官网
-
/ { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp"; }; &gpio{ eeprom_wp{ gpio-hog; gpios = <55 0>; output-low; //low:close wp,high:open wp line-name="eeprom_wp"; }; }; &sdhci0{ no-1-8-v; disable-wp; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 52 0>; sda-gpios = <&gpio 53 0>; eeprom: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <0x1>; #size-cells = <0x1>; }; }; &qspi { flash@0 { compatible = "cy-snor"; /* n25hl512t 64MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <60000000>; /* Based on DC1 spec */ }; }; &spi1 { iam-20680@1{ compatible = "inv,iam20680"; #address-cells = <1>; #size-cells = <1>; reg = <0x1>; spi-max-frequency = <8000000>; }; }; &gem0 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy0: phy@1 { reg = <0x1>; }; }; &pinctrl0 { status = "okay"; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO32", "MIO33", "MIO34", "MIO35", "MIO36", "MIO37"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO26", "MIO27", "MIO28", "MIO29", "MIO30", "MIO31"; bias-disable; low-power-enable; }; /* mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; */ }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_13_grp"; function = "i2c1"; }; conf { groups = "i2c1_13_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_52_grp", "gpio0_53_grp"; function = "gpio0"; }; conf { groups = "gpio0_52_grp", "gpio0_53_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; };