DAY3_ADC调试

使用MCU自带SD24进行信号采集

• Second-order sigma-delta architecture
• Up to seven independent simultaneously sampling ADCs. (The number of channels is device dependent. See
the device-specific data sheet.)
• Fixed 1.024-MHz modulator input frequency
• Software selectable internal or external voltage reference
• Software selectable temperature sensor accessible by all channels

 reference voltage：internal or external 

Modulator Clock：
The clock system generates a 1.024-MHz fixed frequency clock (fM) to the SD24 module. This clock is suppliedto all modulators so that all modulators convert synchronously. This is not a free running clock to the SD24 module—it runs only when an SD24 channel conversion is active.

可见，sd24是多通道可同时采样的adc，关键配置之一是在多通道转换：

                                        Table--->. Conversion Mode Summary

SD24SNGL	SD24GRP	Mode	Operation
1	0	Single channel, single conversion	A single channel is converted once.
0	0	Single channel, continuous conversion	A single channel is converted continuously
1	1	Group of channels, single conversion	A group of channels is converted once.
0	1	Group of channels, continuous conversion	A group of channels is converted continuously

                                                Group of Channels, Single Conversion:
Consecutive SD24 channels can be grouped together with the SD24GRP bit to synchronize conversions. SettingSD24GRP for a channel groups that channel with the next channel in the module. For example, setting SD24GRP for channel 0 groups that channel with channel 1. In this case, channel 1 is the master channel,enabling and disabling conversion of all channels in the group with its SD24SC bit. The SD24GRP bit of the master channel is always 0. The SD24GRP bit of the last channel in SD24 has no function and is always 0.
When SD24SNGL = 1 for a channel in a group, single conversion mode is selected. A single conversion of thatchannel occurs synchronously when the master channel SD24SC bit is set. The SD24SC bit of all channels inthe group are automatically set and cleared by the SD24SC bit of the master channel. SD24SC for each channelcan also be cleared in software independently.
Clearing SD24SC of the master channel before the conversions are completed immediately stops conversions ofall channels in the group, the channels are powered down, and the corresponding digital filters are turned off.
Values in SD24MEMx can change when SD24SC is cleared. It is recommended that the conversion data inSD24MEMx be read prior to clearing SD24SC to avoid reading an invalid result.

Q:

• __delay_cycles的定义同上一篇
• SD24GRP实际定义第一个通道为0，中间为1，最后一通道为0？