4bit扭环形计数器

1.1 verilog HDL code

module twisted_counter(clk,rst_n,dout);
input clk,rst_n;
output reg [3:0] dout;
always@(posedge clk or negedge rst_n)
if(!rst_n) dout <=4’b0000;
else begin
dout<={dout[2:0],~dout[3]};
end
endmodule

1.2 testbench

module twisted_counter_tb;
reg clk,rst_n;
wire [3:0] dout;
twisted_counter U1 (.clk(clk),.rst_n(rst_n),.dout(dout));
always #10 clk=~clk;
initial begin
clk=1’b0;
rst_n=1’b1;
#10 rst_n=1’b0;
#10 rst_n=1’b1;
#100;
end
endmodule

1.3 wave