一个简单的状态机

一个简单的状态机

1.1 简介
有限状态机的方式实现011010序列信号产生器

1.2状态转移图

1.3 verilogHDL 代码

module sequence_signal_fsm(clk,rst_n,dout);
input clk,rst_n;
output reg dout;
reg [2:0] pre_state,next_state;
parameter s0=3’b000,s1=3’b001,s2=3’b010,s3=3’b011,s4=3’b100,s5=3’b101;
always@(posedge clk or negedge rst_n)
if(!rst_n) pre_state<=s0;
else pre_state<=next_state;
always@(pre_state)
case(pre_state)
s0:begin dout<=1’b0; next_state<=s1; end
s1:begin dout<=1’b1; next_state<=s2; end
s2:begin dout<=1’b1; next_state<=s3; end
s3:begin dout<=1’b0; next_state<=s4; end
s4:begin dout<=1’b0; next_state<=s5; end
s5:begin dout<=1’b1; next_state<=s0; end
default next_state<=s0;
endcase
endmodule

1.4 testbench

`timescale 1ns/1ns
module sequence_signal_fsm_tb;
reg clk,rst_n;
wire dout;
sequence_signal_fsm U1(.clk(clk),.rst_n(rst_n),.dout(dout));
always #10 clk=~clk;
initial begin
clk=1’b0;
rst_n=1’b1;
#5 rst_n=1’b0;
#5 rst_n=1’b1;
end
endmodule