奇偶校验器

奇偶校验器

1.1 简介

8bit 奇偶校验器。

1.2 verilog代码

module odd_even_check(din,d_odd,d_even);
	input [7:0] din;
	output d_odd,d_even;
	assign d_odd=^din;
	assign d_even=~d_odd;
endmodule

1.3 testbench

`timescale 1ns/1ns
module odd_even_check_tb;
	reg [7:0] din;
	reg clk;
	wire d_odd,d_even;
	odd_even_check U1(.din(din),.d_odd(d_odd),.d_even(d_even));
	always #10 clk=~clk;
	initial begin
		clk=1'b0;
		end
	always@(posedge clk)	
		din=1+$random()%254;
endmodule

1.4 wave