9 异步复位同步释放
Verilog代码:
module arsr( // Asynchronous reset synchronous release
input clk,
input rst,
input din,
output reg dout
);
reg tmp;
reg reset;
always@(posedge clk or negedge rst) begin
if(!rst) begin
tmp <= 0;
reset <= 0;
end
else begin
tmp <= 1;
reset <= tmp;
end
end
always@(posedge clk or negedge reset) begin
if(!reset)
dout <= 0;
else
dout <= din;
end
endmodule