手撕Verilog面试题专题——（3）串并转换

3 串并转换

Verilog代码：

module SerialToParallel(
	input			clk,
	input 			rst,
	input			din,
	output	[7:0]	dout
);
	reg	[7:0]	tmp;
	always@(posedge clk or negedge rst)	begin
		if(!rst)
			tmp	<= 0;
		else
			tmp	<= {tmp[6:0], din};
	end
	assign dout	= tmp;
endmodule

testbench仿真文件：

module SerialToParallel_tb();

	parameter	[15:0]	data = 16'b1010_1101_0101_1011;
	reg				clk;
	reg 			rst;
	reg				din;
	reg		[3:0]	count;
	wire	[7:0]	dout;
	initial begin
		clk = 0;
		rst = 0;
		#10 rst = 1;
	end
	initial begin
		forever #4 clk = ~clk;
	end

	always@(posedge clk or negedge rst)	begin
		if(!rst)	begin
			din		<= 0;
			count	<= 0;
		end
		else	begin
			din		<= data[count];
			count	<= count + 1;
		end
	end
	
	SerialToParallel stp(
	.clk(clk),
	.rst(rst),
	.din(din),
	.dout(dout)
	);
	
endmodule

仿真波形：